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Design and Implementation of Time Synchronizer for Advanced ZigBee Systems

개선된 지그비 시스템을 위한 시간 동기부 설계 및 구현

  • Hwang, Hyunsu (School of Electronics and Information Eng., Korea Aerospace University) ;
  • Jung, Yongcheol (School of Electronics and Information Eng., Korea Aerospace University) ;
  • Jung, Yunho (School of Electronics and Information Eng., Korea Aerospace University)
  • 황현수 (한국항공대학교 항공전자정보공학부) ;
  • 정용철 (한국항공대학교 항공전자정보공학부) ;
  • 정윤호 (한국항공대학교 항공전자정보공학부)
  • Received : 2016.09.09
  • Accepted : 2016.10.25
  • Published : 2016.10.30

Abstract

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. Therefore, advanced ZigBee (AZB) systems that support the various data rate under 250 kbps are proposed. However, the preamble structure for AZB systems causes the complexity increase of time synchronization circuits. In this paper, we propose preamble structure and time synchronization algorithm which can solve the problem of the complexity increase of time synchronization circuits. Implementation results show that the proposed time synchronizer for AZB systems include the logic slices of 6.92 k and, which are reduced at the rate of 62.3% compared with existing architecture.

최근 다양한 센서를 활용하는 응용분야의 증가로 인해 가변전송률을 지원하는 무선 통신 시스템의 필요성이 증가하고 있다. 이에 IEEE 802.15.4 ZigBee 시스템을 개량하여 250 kbps이하의 다양한 가변전송률을 지원하는 AZB (advanced ZigBee) 시스템이 제안 되었다. AZB 시스템은 250 kbps 이하 125 kbps, 62.5 kbps, 31.25 kbps의 가변 전송률을 지원할 수 있는 프리앰블 구조를 정의하였는데, 정의된 프리앰블 구조로 인해 AZB 시스템의 시간동기부의 회로 면적이 급격히 증가하는 문제점이 발생한다. 이에, 본 논문에서는 가변 전송률을 지원하면서도 시간동기부의 회로면적을 감소시킬 수 있는 새로운 프리앰블 구조 및 시간 동기 획득 알고리즘을 제안한다. 제안된 시간 동기부는 6.92 k의 FPGA (field programmable gate array) logic slices 합성되었고, 기존 구조 대비 62.3 % 복잡도 감소를 보였다.

Keywords

References

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