• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.1
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• pp.67-76
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• 2012

Due to the increasing amount of applications of power electronic ac-dc converters, it is necessary to design a single-stage converter that can reliably perform both buck and boost operations. Traditionally, this can be achieved by double-stage conversion (ac/dc-dc/dc) which ultimately leads to less efficiency and a more complex control system. This paper discusses two types of modern ac-dc converters. First, the novel impedance-source ac-dc converter, abbreviated as custom Z-source rectifier, is analyzed; and then, switched inductor (SL) Z-source ac-dc converter is proposed. This paper describes the Z-source rectifiers' operating principles, the concepts behind them, and their superiorities. Analysis and simulation results show that the proposed custom Z-source rectifier can step up and step down voltage; and the main advantage of the SL Z-source ac-dc converter is its high step-up capability. Low ripple of the output dc voltage is the other advantage of the proposed converters. Finally, the SL Z-source ac-dc converter is compared with the custom Z-source ac-dc converter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.113-115
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• 2008

At the high speed operation, the high demagnetization voltage can reduce the negative torque, so the output power and efficiency can be improved. In this paper, a novel power converter for single phase SRM with high demagnetization voltage is proposed. A simple passive capacitor circuit is added in the front-end, which consists of three diodes and one capacitor. Based on this passive network, the two capacitors can be connected in series and parallel, so the phase winding of SRM obtains general do-link voltage in excitation mode and the double dc-link voltage in demagnetization mode. The operation modes of the proposed converter are analyzed in detail. Some computer simulation results is done to verify the performance of proposed converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.167-174
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• 2015

This study describes how digital time delay deteriorates control performance in zero voltage switching (ZVS) phase-shifted full bridge (PSFB) converter. The small-signal model of the ZVS PSFB converter is derived from the buck-converter small-signal model. Digital time delay effects have been considered according to the digital sampling methods. The analysis verifies that digital time delays reduce the stability margin of the converter, and the double sampling technique exhibits better performance than the single sampling technique. Both simulation and experimental results based on 250 W ZVS PSFB confirm the validity of the analyses performed in the study.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.879-880
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• 2008

At the high speed operation, the boost negative bias can reduce the negative torque and increase the dwell angle, so the output power and efficiency can be improved. In this paper, a novel power converter for single phase SRM with boost negative bias is proposed. A simple passive capacitor circuit is added in the front-end, which consists of three diodes and one capacitor. Based on this passive capacitor network, the two capacitors can be connected in series and parallel in different condition. In proposed converter, the phase winding of SRM obtains general dc-link voltage in excitation mode and the double dc-link voltage in demagnetization mode. The operation modes of the proposed converter are analyzed in detail. Some computer simulation and experimental results are done to verify the performance of proposed converter.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1149-1157
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• 2015

As a key part in the wind turbine system, the power electronic converter is proven to have high failure rates. At the same time, the failure of the wind power converter is becoming more unacceptable because of the quick growth in capacity, remote locations to reach, and strong impact to the power grid. As a result, the correct assessment of reliable performance for power electronics is a crucial and emerging need; the assessment is essential for design improvement, as well as for the extension of converter lifetime and reduction of energy cost. Unfortunately, there still exists a lack of suitable physic-of-failure based evaluation tools for a reliability assessment in power electronics. In this paper, an advanced tool structure which can acquire various reliability metrics of wind power converter is proposed. The tool is based on failure mechanisms in critical components of the system and mission profiles in wind turbines. Potential methodologies, challenges, and technology trends involved in this tool structure are also discussed. Finally, a simplified version of the tool is demonstrated on a wind power converter based on Double Fed Induction Generator system. With the proposed tool structure, more detailed information of reliability performances in a wind power converter can be obtained before the converter can actually fail in the field and many potential research topics can also be initiated.

• Journal of Power Electronics
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• v.12 no.3
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• pp.410-417
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• 2012

In this paper, a direct current control method based on a one-cycle controller (DCOCC) for double frequency buck converters (DF buck) is proposed. This control method can make the average current through the high frequency and low frequency inductors of a DF buck converter equal. This is similar to the average current control method. However, the design of the loop compensator is much easier when compared with the average current control. Since the average current though the high frequency and low frequency inductors is equivalent, the current stress of the high frequency switches and the switch losses are minimized. Therefore, the efficiency of the DF buck converter is improved. Firstly, the operation principle of DCOCC is described, then the small signal models of a one cycle controller and a DF buck converter are presented based on the state space average method. Eventually, a system block diagram of the DCOCC controlled DF buck is established and the compensator is designed. Finally, simulation and experiment results are given to verify the correction of the theory analysis.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• Journal of the Korean Institute of Gas
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• v.3 no.2 s.7
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• pp.70-76
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• 1999

Because of the tight pollution control of $SO_2$ emission, sulfuric acid manufacturers have been interested in the operation with the highest possible conversion efficiency. In this work, the design criteria and operating conditions of the catalytic converter were investigated for maximum conversion efficiency and minimum $SO_2$ emission by parametric analysis and process optimization for the existing acid plants. The Double Converter/Double Absorber(DC/DA) process was investigated by varying $SO_2$ compositions of feed gas, pressures and temperatures of layers of the converter and the depth of the catalyst beds. In order to evaluate the process, a computer simulator for sulfuric acid plants has been developed. The results by process optimization could be used for the converter design and operating conditions with highest conversion efficiency.