• Journal of Sensor Science and Technology
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• v.14 no.4
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• pp.272-277
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• 2005

A CMOS active pixel sensor has been designed and fabricated using standard 2-poly and 4-metal $0.35{\mu}m$ CMOS processing technology. The CMOS active pixel sensor has been made up of a unit pixel having a highly sensitive PMOSFET photo-detector and electronic shutters that can control the light exposure time to the PMOSFET photo-detector, correlated-double sampling (CDS) circuits, and an 8-bit two-step flash analog to digital converter (ADC) for digital output. This sensor can obtain a stable photo signal in a wide range of light intensity. It can be realized with a special function of an electronic shutter which controls the light exposure-time in the pixel. Moreover, this sensor had obtained the digital output using an embedded ADC for the system integration. The designed and fabricated image sensor has been implemented as a $128{\times}128$ pixel array. The area of the unit pixel is $7.60{\mu}m{\times}7.85{\mu}m$ and its fill factor is about 35 %.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1406-1409
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• 2004

The Resolver usually used in industry is the absolute angle analog sensor that must be in order to driving BLDC (brushless DC) motor, and it needs RDC(Resolver-to-Digital converter) for changing the output signal to digital to be applied to the SVPWM(Space Vector Pulse Width Modulation) algorithm. Commonly used S/W RDC needs trigonometric function. What it takes a lot of calculation time of processor is gotten at weak point. In this paper, S/W RDC is realized except trigonometric functions as a result of feedback resolver outputs after filtering using FIR filter. thus, processing time is reduced. So, One-chip DSP Controller operating the Vector Control, RDC, and SVPWM can be designed.

• The Magazine of the IEIE
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• v.38 no.1
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• pp.56-67
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• 2011

As a result of quickly growing data, a digital transmission system is required to deal with the challenge of acquiring signals at a very high sampling rate, Fortunately, the CS (Compressed Sensing or Compressive Sensing) theory, a new concept based on theoretical results of signal reconstruction, can be employed to exploit the sparsity of the received signals. Then, they can be adequately reconstructed from a set of their random projections, leading to dramatic reduction in the sampling rate and in the use of ADC (Analog-to-Digital Converter) resources. The goal of this article is provide an overview of the basic CS theory and to survey some important compressed sensing applications in wireless communications.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.1
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• pp.13-20
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• 2012

This paper proposes a marine engine state monitoring system using a DPQ (Distributed Precedence Queue) mechanism which collects the state of bearings, temperature and pressure of engine through the CAN network. The CAN is developed by Bosch Corp. in the early 1980' for automobile network. The data from various sensors attached in the marine engine are converted to digital by the analog to digital converter and formatted to fit the CAN protocol at the CAN module. All the CAN modules are connected to the SPU (Signal Processing Unit) module for the efficient communication and processing. This design reduces the cost for wiring and improves the data transmission reliability by recognizing the sensor errors and data transmission errors. The DPQ mechanism is newly developed for the performance improvement of the marine engine system, which is demonstrated through the experiments.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.227-228
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• 2007

The dynamic range of the radar which uses digital signal processors is limited by ADC(analog- to-digital converter). This parameter and ADC loss depend on the noise level of radar receivers. In order to stabilize the performance of radar systems, it is necessary to maintain the noise level constantly. This paper presents a noise AGC(automatic gain control) concept that can keep the noise level constantly and proves that the concept is acceptable through evaluation and hardware test.

• Journal of IKEEE
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• v.26 no.2
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• pp.299-305
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• 2022

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.460-465
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• 2007

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB{\sim}-0.63LSB$ and $0.53LSB{\sim}-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.