Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

Low-Power Sigma-Delta ADC for Sensor System

센서 시스템을 위한 저전력 시그마-델타 ADC

  • Shin, Seung-Woo (Dept. of Electrical and Computer Engineering, University of Seoul) ;
  • Kwon, Ki-Baek (Dept. of Electrical and Computer Engineering, University of Seoul) ;
  • Park, Sang-Soon (Dept. of Electrical and Computer Engineering, University of Seoul) ;
  • Choi, Joogho (Dept. of Electrical and Computer Engineering, University of Seoul)
  • Received : 2022.05.25
  • Accepted : 2022.06.21
  • Published : 2022.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

다양한 물리적 신호를 디지털 신호 영역에서 처리하기 위해서 센서의 출력을 디지털로 변환하는 아날로그-디지털 변환기 (ADC)는 시스템 구성에 있어 매우 중요한 구성 블록이다. 센서 신호 처리를 위한 아날로그 회로의 역할을 디지털로 변환하는 추세에 따라 이러한 ADC의 해상도는 높아지는 추세이다. 또한 ADC는 모바일 기기의 배터리 효율 증대를 위해서 저전력 성능이 요구된다. 기존 integrating 시그마-델타 ADC의 경우 고해상도를 가지는 특징이 있지만, 저전압 조건과 미세화 공정으로 인해 적분기의 연산증폭기 이득 오차가 증가해 정확도가 낮아지게 된다. 이득 오차를 최소화하기 위해 버퍼 보상 기법을 적용할 수 있지만 버퍼의 전류가 추가된다는 단점이 있다. 본 논문에서는 이와 같은 단점을 보완하고자 버퍼를 스위칭하며 전류를 최소화시키고, 하이패스 바이어스 회로를 통해 settling time을 향상시켜 기존과 동일한 해상도를 갖는 ADC를 설계하였다.

Keywords

Acknowledgement

This work was supported by the 2020 Research Fund of the University of Seoul.

References

  1. J. Silva, U. Moon, J. Steensgaard and G. C. Temes, "Wideband low distortion delta sigma ADC topology," Electronics Letters, vol.37, no.12, pp.737-738, 2001. DOI: 10.1049/el:20010542
  2. Jos'e M. de la Rosa and Roc'io del R'io, "Press, CMOS Sigma-Delta Converters: Practical Design Guide," Wiley-IEEE Press, 2013.
  3. Youngho Jung, "Derivation of design equations for various incremental delta sigma analog to digital converters," Journal of the Korea Institute of Information and Communication Engineering, Vol.25, No.11, pp.1619-1626, 2021. DOI: 10.6109/jkiice.2021.25.11.1619
  4. Baschirotto, A. and Chironi, V. and Cocciolo, G. and D'Amico, S. and De Matteis, M. and Delizia, P. "Low Power Analog Design in Scaled Technologies", Topical Workshop on Electronics for Particle Physics, 2009, pp.103-109.
  5. Chulkyu Park, "High-Accuracy Analog Front-End Compensation Technique for Mobile Sensor Applications," Ph.D. dissertation, University of Seoul, Seoul, Korea, 2018.
  6. Jeong Tae-kyung, "Low-Power Integrating Sigma-Delta ADC for instrumentation Applications", Master thesis, University of Seoul, Seoul, Korea, 2020.
  7. P. M. Figueiredo and J. C. Vital, 2004, "Low kickback noise techniques for CMOS latched comparators," IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-537-540, 2004. DOI: 10.1109/ISCAS.2004.1328250
  8. Y. M. Chi and G. Cauwenberghs, "Micropower integrated bioamplifier and auto-ranging ADC for wireless and implantable medical instrumentation," 2010 Proceedings of ESSCIRC, pp.334-337, 2010. DOI: 10.1109/ESSCIRC.2010.5619711
  9. J. Garcia, S. Rodriguez and A. Rusu, "A Low-Power CT Incremental 3rd Order Sigma Delta ADC for Biosensor Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.60, no.1, pp.25-36, 2012. DOI: 10.1109/TCSI.2012.2215753
  10. W. Yu, M. Aslan and G. C. Temes, "82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction," IEEE Custom Integrated Circuits Conference 2010, 2010. DOI: 10.1109/CICC.2010.5617596
  11. S. Tao and A. Rusu, "A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.62, no.6, pp.1489-1498, 2015. DOI: 10.1109/TCSI.2015.2418892