• Proceedings of the KIEE Conference
• /
• 2003.07d
• /
• pp.2717-2719
• /
• 2003

In this paper, we developed an efficient virtual experiment kit with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since our virtual experiment kit is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, our web-based virtual experiment kit is designed to enhance the efficiency of both the learners and the educators. The learners will be able to achieve high learning standard and the educators save time and labor. The virtual experiment is performed according to the following procedure: (1) Circuit Composition on the Bread Board (2) Applying Input Voltage (3) Output Measurements (4) Checkout of Experiment Results. Furthermore, the circuit composition on the bread board and its corresponding online schematic diagram are displayed together on the virtual experiment kit for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.

• The KIPS Transactions:PartA
• /
• v.10A no.3
• /
• pp.255-260
• /
• 2003

In recent, as a typical example of RFID, the contactless IC card is widely used in traffic, access control system and so forth. And its use becomes a general tendency more and more because of the development of RF technology and improvement of requirement for user convenience. This paper describes the hardware module to process embedded contactless protocol for implementation contactless IC card. And the hardware module consists of analog circuits and specific digital logic circuits. This paper also describes more effective design method of contactless IC card, which method separates into analog circuit parts, digital logic circuit part, and software parts according to the role of the design parts.

• ETRI Journal
• /
• v.36 no.1
• /
• pp.89-98
• /
• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• 전자공학회논문지 IE
• /
• v.45 no.3
• /
• pp.5-12
• /
• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• Proceedings of the KAIS Fall Conference
• /
• 2009.12a
• /
• pp.636-639
• /
• 2009

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Proceedings of the KIEE Conference
• /
• 1993.07a
• /
• pp.501-503
• /
• 1993

A circuit of sigmoid function for neural network is designed by using Piecewise Linear (PWL) method. The slope of sigmoid function can be adjusted to 2 and 0.25. Also the circuit presents both sigmoid function and its differential form. The circuits is simulated by using ViewLogic. Theoretical and simulated performance agree with 1.8 percent.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.622-634
• /
• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• Progress in Superconductivity
• /
• v.7 no.2
• /
• pp.109-113
• /
• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.3
• /
• pp.327-339
• /
• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.1-10
• /
• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.