Journal of the Korean Institute of Telematics and Electronics (대한전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A SDL Hardware Compiler for VLSI Logic Design Automation

VLSI의 논리설계 자동화를 위한 SDL 하드웨어 컴파일러

  • Cho, Joung Hwee (Dept. of Elec. Eng., Hanyang Univ.) ;
  • Chong, Jong Wha (Dept. of Elec. Eng., Hanyang Univ.)
  • 조중휘 (한양대학교 전자공학과) ;
  • 정정화 (한양대학교 전자공학과)
  • Published : 1986.03.01
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Abstract

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

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