• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권1호
• /
• pp.15-19
• /
• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• 센서학회지
• /
• 제15권4호
• /
• pp.245-250
• /
• 2006

In this paper, glass cap wafer for MEMS device package is fabricated by using sand blaster dry etcher and Its surface is studied. The surface of dry etched glass is analyzed by using SEM, and many glass particles and micro cracks are observed. If these kind of particles were dropped from glass to the surface of device, It would make critical failure to the operation of device. So, several cleaning and etching methods are induced to remove these kinds of dormant failure mode and optimized condition is found out.

• 대한기계학회논문집A
• /
• 제29권9호
• /
• pp.1276-1281
• /
• 2005

Compound semiconductors are the semiconductors composed of more than two chemical elements. Lithium Tantalate$K_I$ wafer is used for several optical devices, especially surface acoustic wave(SAW) device. Because of the lithography in SAW device process, $LiTaO_3$ polishing is needed. In this paper, the commercial slurries $(NALC02371^{TM},\; ILD1300^{TM},\;ceria slurry)$ used for chemical mechanical polishing(CMP) were tested, and the most suitable slurry was selected by measuring material removal rate and average centerline roughness$(R_a)$. From these result, it was proven that $ILD1300^{TM}$ was the most suitable slurry for $LiTaO_3$ wafer CMP due to the chemical reaction between solution in slurry and material.

• 반도체디스플레이기술학회지
• /
• 제15권3호
• /
• pp.72-77
• /
• 2016

As the semiconductor production technology has gradually developed and intra-market competition has grown fiercer, the caliber of Si Wafer for semiconductor production has increased as well. And semiconductors have become integrated with higher density. Presently the Si Wafer caliber has reached up to 450 mm and relevant production technology has been advanced together. Electrostatic chuck is an important device utilized not only for the Wafer transport and fixation but also for the heat treatment process based on plasma. To effectively control the high calories generated by plasma, it employs a refrigerant-based cooling method. Amid the enlarging Si Wafers and semiconductor device integration, effective temperature control is essential. Therefore, uniformed temperature distribution in the electrostatic chuck is a key factor determining its performance. In this study, the form of refrigerant flow channel will be investigated for uniformed temperature distribution in electrostatic chuck.

• 전기의세계
• /
• 제34권3호
• /
• pp.141-144
• /
• 1985

다이리스터는 power semiconduct or device중에서 가장 광범위 또한 대용량의 전류와 전압을 취급할 수 있는 소자로써 널리이용되고 있다. 또한 silicon wafer의 크기가 증가하고 있기때문에 전류의 증가가 기대가 되고 있다. 그러나 MOSFEF의 power device의 응용이 증가되고 있으나 대용량의 전류와 전압의 조절분야에서는 다이리스터의 역할을 두드러질 것이다.

• 한국세라믹학회지
• /
• 제34권7호
• /
• pp.699-702
• /
• 1997

The cross sectional image of thin oxide failure of MOS device could be observed by Emission Microscope and Focused Ion Beam at the weak point. The oxide failures in low electric field was associated with the presence of a particle or abnormal pattern. The failures occuring at medium field are related to a pit of Si substrate. The pits could be originated from the microdefects of Cz Si wafer.

• 전자공학회논문지A
• /
• 제30A권11호
• /
• pp.99-104
• /
• 1993

We analyzed the D.I. water used in wet cleaning process of semiconductor device manufacturing both at the D.I. water plant and at the wafer cleaning bath to detect the impurity source of D.I. water contamination. This shows that the quantity of impurity is related to the resistivity of D.I. water, and we found that the cleanliness of the wafer surface processed in D.I. water bath was affected by the degree of the ionic impurity contamination. So we evaluated the cleaning effect as different method for Fe ion, having the best adsoptivity on wafer surface. Moreover the temperature effect of the D.I. water is investigated in case of anion in order to remove the chemical residue after wet process. In addition to the control of D.I. water resistivity, chemical analysis of impurity control in D.I. water should be included and a suitable cleaning an drinsing method needs to be investigated for a high yielding semiconductor device.

• 한국전기전자재료학회논문지
• /
• 제18권12호
• /
• pp.1075-1079
• /
• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• Journal of Magnetics
• /
• 제10권2호
• /
• pp.41-43
• /
• 2005

We have investigated an optical waveguide isolator with a multimode interference section by wafer direct bonding, operating at a wavelength $1.55\;{\mu}m$. In order to fabricate the device for monolithic integration, the wafer direct bonding between a magnetic garnet material as a cladding layer and a semiconductor guiding layer has been achieved. We found that wafer direct bonding between InP and GGG $(Gd_3Ga_5O_{12})$ is effective for the integration of a waveguide optical isolator. The isolation ratio was obtained to be 2.9 dB in the device.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2011년도 제42회 하계학술대회
• /
• pp.1702-1703
• /
• 2011

MEMS 소자의 Wafer level Package 관련하여 Deep cavity를 가진 Cap Wafer와 Polymer bonding 중 cavity 단차로 인한 Polymer Patterning 및 접합 불량의 어려움을 극복할 수 있는 새로운 공정 flow를 제안하였다. Cavity를 형성할 때 사용하는 Si deep etching Mask인 기존의 Photoresist를 접합용 감광성 Polymer로 대체하고, cavity 형성 후, 별도의 추가 공정 없이 이 Polymer를 이용해 Wafer bonding을 진행하였다. 이를 통해 cavity 단차에 따른 문제를 해결함과 동시에 공정이 단순하고 제작 비용이 저렴하며, 신뢰성 있는 Wafer level Package를 구현하였다.