• Title/Summary/Keyword: DLL4

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A Multiphase Compensation Method with Dynamic Element Matching Technique in Σ-Δ Fractional-N Frequency Synthesizers

  • Chen, Zuow-Zun;Lee, Tai-Cheng
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.3
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    • pp.179-192
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    • 2008
  • A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

A CMOS Impulse Radio Ultra-Wideband Receiver for Inner/Inter-chip Wireless Interconnection

  • Nguyen, Chi Nhan;Duong, Hoai Nghia;Dinh, Van Anh
    • Journal of IKEEE
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    • v.17 no.2
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    • pp.176-181
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    • 2013
  • This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.

A New Approach to CAD/CAM Systems Data Exchange Using Plug-in Technology

  • Chernopyatov Y.A.;Chung W.j.;Lee C.M.
    • International Journal of Precision Engineering and Manufacturing
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    • v.6 no.4
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    • pp.8-13
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    • 2005
  • Interoperability has been the problem of CAD/CAM systems. Starting from 1980's, national and international organizations have addressed the issue through development and release of standards for the exchange of geometric and nongeometric design data. To CAD/CAM vendors, the task of interpreting and implementing these standards falls into their products. This task is a balancing action between users' needs, available development resources, and the technical specifications of standards. This paper explores an area of CAD/CAM systems development, particularly the implementation of the effective exchange files translators'. A new approach is introduced, which proposes to enclose all the translation operations concerning each exchange format to a separate DLL, thus making a 'plug-in.' Then, this plug-in could be used together with the CAD/CAM system or with specialized translation software. This approach allows to create new translators rapidly and to gain the reliable, high-efficiency, and reusable program code. The second part of the paper concerns the possible problems of translators' development. These difficulties often come from the exchange standards' misunderstanding or ambiguity in standards. All examples come from the authors' practice experiences of dealing with CAD/CAM systems.

The Usefulness of MRCP in the Evaluation of Pancreaticobiliary Diseases in Children (소아에서 담췌관 질환에 대한 자기공명 담췌관조영술의 진단적 유용성)

  • Uhm, Ji Hyun;Lee, Seung Yeon;Chung, Ki Sup
    • Clinical and Experimental Pediatrics
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    • v.45 no.11
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    • pp.1381-1388
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    • 2002
  • Purpose : Magnetic resonance cholangiopancreatography(MRCP) is a noninvasive method for imaging the pancreaticobiliary tree. The aim of this study was to evalute the usefulness of MRCP for the diagnosis of pancreaticobiliary diseases in children. Methods : From October 1996 to May 2001, 67 patients with obstructive jaundice and three patients with chronic recurrent pancreatitis were evaluated with abdominal ultrasonography and MRCP. The final diagnosis was based on the operative and pathologic findings with biopsy specimen including clinical and laboratory findings. Results : A total of 70 patients, consisting of 31 males and 39 females, with a mean age of $2.6{\pm}3.3$ years were studied. The final diagnosis was biliary atresia in 25, neonatal cholestasis in 18, choledochal cyst without anomalous pancreatobiliary duct union(APBDU) in nine, choledochal cyst with APBDU in seven, cholestatic hepatitis in five, chronic recurrent pancreatitis in three, sclerosing cholangitis in two, and secondary biliary cirrhosis in one case. The overall diagnostic accuracy of abdominal ultrasonography was 75.7% and that of MRCP was 97.1%. The sensitivity and specificity of MRCP were 100% and 98% for biliary atresia, 87.5% and 100% for choledochal cyst with APBDU, 100% and 100% for choledochal cyst without APBDU, sclerosing cholangitis and chronic recurrent pancreatitis, respectively. Conclusion : MRCP is a fast, non-invasive and reliable method for diagnosing pancreaticobiliary diseases in children and will be the standard diagnostic procedure in the future.

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

  • Zhang, Changchun;Li, Ming;Wang, Zhigong;Yin, Kuiying;Deng, Qing;Guo, Yufeng;Cao, Zhengjun;Liu, Leilei
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.4
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    • pp.303-317
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    • 2013
  • Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

Low Power Serial Interface I/O by using Phase Modulation (위상변조를 이용한 저 전력 입출력 인터페이스 회로)

  • Park, Hyung-Min;Kang, Jin-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.2
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    • pp.1-6
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    • 2011
  • This paper describes a phase modulation I/O (PMIO) serial interface circuit that supports 1Gbps transfer rate with 12mW power consumption at 1.2V supply. The proposed PMIO which consists of TX and RX blocks utilizes a phase modulation technique. The rising edge is fixed to get the clock phase information and falling edge has multi positions for the multi-data information to increase the transfer rate. The designed circuit use the 16 possible falling edge positions. The data transfer rate is four times faster than the clock rate. The circuit has been implemented using $0.13{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of transfer data (phase data) and recovery data.

Code synchronization technique for spread spectrum transmission based on DVB-RCS +M standard (DVB-RCS +M 표준기반의 대역확산기술 부호동기기법)

  • Kim, Pan-Soo;Chang, Dae-Ig;Lee, Ho-Jin
    • Journal of Satellite, Information and Communications
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    • v.4 no.2
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    • pp.39-45
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    • 2009
  • This paper proposes the specific code synchronization technique for DS-SS(Direct Sequence-Spread Spectrum transmission in the DVB-RCS +M standard. DS-SS is better than multi-carrier transmission method under nonlinear channel but imposes a long acquisition time. To improve the synchronization aspect, the robust correlation structure is introduced for acquisition and the nonlinear delay lock loop is done for tracking. MAT(Mean Acquisition Time) performances is shown to validate its superiority. In addition, code tracking and jitter performances are done when code tracking algorithm based on 2 oversamples which is not influenced by sampling clock timing offset and carrier freq. offset is used.

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Antifuse Circuits and Their Applicatoins to Post-Package of DRAMs

  • Wee, Jae-Kyung;Kook, Jeong-Hoon;Kim, Se-Jun;Hong, Sang-Hoon;Ahn, Jin-Hong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.4
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    • pp.216-231
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    • 2001
  • Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

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MPEG-H 3D Audio Decoder Structure and Complexity Analysis (MPEG-H 3D 오디오 표준 복호화기 구조 및 연산량 분석)

  • Moon, Hyeongi;Park, Young-cheol;Lee, Yong Ju;Whang, Young-soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.42 no.2
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    • pp.432-443
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    • 2017
  • The primary goal of the MPEG-H 3D Audio standard is to provide immersive audio environments for high-resolution broadcasting services such as UHDTV. This standard incorporates a wide range of technologies such as encoding/decoding technology for multi-channel/object/scene-based signal, rendering technology for providing 3D audio in various playback environments, and post-processing technology. The reference software decoder of this standard is a structure combining several modules and can operate in various modes. Each module is composed of independent executable files and executed sequentially, real time decoding is impossible. In this paper, we make DLL library of the core decoder, format converter, object renderer, and binaural renderer of the standard and integrate them to enable frame-based decoding. In addition, by measuring the computation complexity of each mode of the MPEG-H 3D-Audio decoder, this paper also provides a reference for selecting the appropriate decoding mode for various hardware platforms. As a result of the computational complexity measurement, the low complexity profiles included in Korean broadcasting standard has a computation complexity of 2.8 times to 12.4 times that of the QMF synthesis operation in case of rendering as a channel signals, and it has a computation complexity of 4.1 times to 15.3 times of the QMF synthesis operation in case of rendering as a binaural signals.

Dietary corn resistant starch regulates intestinal morphology and barrier functions by activating the Notch signaling pathway of broilers

  • Zhang, Yingying;Liu, Yingsen;Li, Jiaolong;Xing, Tong;Jiang, Yun;Zhang, Lin;Gao, Feng
    • Asian-Australasian Journal of Animal Sciences
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    • v.33 no.12
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    • pp.2008-2020
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    • 2020
  • Objective: This study was conducted to investigate the effects of dietary corn resistant starch (RS) on the intestinal morphology and barrier functions of broilers. Methods: A total of 320 one-day-old broilers were randomly allocated to 5 dietary treatments: one normal corn-soybean (NC) diet, one corn-soybean-based diet supplementation with 20% corn starch (CS), and 3 corn-soybean-based diets supplementation with 4%, 8%, and 12% corn resistant starch (RS) (identified as 4% RS, 8% RS, and 12% RS, respectively). Each group had eight replicates with eight broilers per replicate. After 21 days feeding, one bird with a body weight (BW) close to the average BW of their replicate was selected and slaughtered. The samples of duodenum, jejunum, ileum, caecum digesta, and blood were collected. Results: Birds fed 4% RS, 8% RS and 12% RS diets showed lower feed intake, BW gain, jejunal villus height (VH), duodenal crypt depth (CD), jejunal VH/CD ratio, duodenal goblet cell density as well as mucin1 mRNA expressions compared to the NC group, but showed higher concentrations of cecal acetic acid and butyric acid, percentage of jejunal proliferating cell nuclear antigen-positive cells and delta like canonical Notch ligand 4 (Dll4), and hes family bHLH transcription factor 1 mRNA expressions. However, there were no differences on the plasma diamine oxidase activity and D-lactic acid concentration among all groups. Conclusion: These findings suggested that RS could suppress intestinal morphology and barrier functions by activating Notch pathway and inhibiting the development of goblet cells, resulting in decreased mucins and tight junction mRNA expression.