• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1062-1069
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• 2013

This paper proposes a simple current compensation method to improve the control performance of B4 inverters. Four-switch inverters so called B4 inverters employ only four switches. They have a split dc-link and one phase of three-phase motors is connected to the center-tap of split dc-link capacitors in B4 inverters. The voltage ripples in the center tap of the dc-link generate unbalanced three-phase voltages causing current ripples. To solve this problem, this paper presents a simple compensation method that adjusts switching times considering dc-link voltage ripples. The validity of the proposed method is verified by simulations and experiments carried out with a 1 HP induction machine.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.207-210
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• 2002

This paper describes a design of multiple-mode single-output DC/DC converter which can be used in both up and down conversion. Proposed up/down converter does not produce a negative voltage which is generated in conventional buck-boost type converter. Three types of operation mode(up/down/bypass) are controlled by the input voltage sense and command signals of target output voltage. PFM(pulse frequency modulation) control is adopted and modified for fast tracking and for precise output voltage level with an aid of output voltage sense. Designed DC/DC converter has the performance of less than 5 % ripple and higher than 80 % efficiency. Chip area is 3.50 mm ${\times}$ 2.05 mm with standard 0.35 $\mu\textrm{m}$ CMOS technology.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.2018-2030
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• 2015

A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal reference-random carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA).

• Journal of Power Electronics
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• 제16권3호
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• pp.1122-1130
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• 2016

This paper presents a novel approach for achieving both a tight DC voltage regulation and a power factor control by applying the Reaching Law Sliding Mode Control (RL-SMC) and the conventional Sliding Mode Control (SMC). Applying these strategies on a matrix rectifier (MR) can achieve a unity grid side power factor when the DC load changes widely and it can provide a ripple-free output voltage that is easily affected by distortions of the three-phase ac voltage supply. Furthermore, by employing the reaching law on the SMC can solve the chatting problem of the sliding motion. Comparative Matlab simulations and experimental verifications for these strategies have been presented and discussed in this paper. The results show that by applying the SMC and RL-SMC on a MR can achieve a unity grid side power factor and a regulated ripple-free DC output.

• Journal of Electrical Engineering and Technology
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• 제5권2호
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• pp.290-298
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• 2010

This paper proposes an adaptive carrier-based pulse width modulation (PWM) method for a four-switch three-phase (4S3P) inverter under dc-link voltage ripple conditions. The proposed method guarantees balanced output currents despite of the existence of the voltage oscillations across two dc-link capacitors. And also, this new approach achieves a linear over-modulation with calculation time reduction. Simulation and experimental results are given to validate the feasibility of the proposed method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• 전력전자학회논문지
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• 제3권3호
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• pp.191-198
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• 1998

본 논문에서는 브러시리스 직류 전동기의 상 전류 제어를 위해 유니폴라 PWM 방식이 적용될 때 상 전환에 의한 토크 맥동을 저감시키기 위한 새로운 전류 제어 방식을 제안한다. 상 전환은 통전된 상의 평균 전압의 순간적인 변동을 야기시켜 전류에 맥동을 발생시키고, 이 맥동 전류는 토크 맥동을 발생시킨다. 본 논문에서는 PWM 패턴에 따를 전환 구간에서의 통전된 상의 평균 전압 변화를 분석하고 평균 전압 변동을 보상하기 위한 전류 제어기를 설계한다. 그리고 실험 결과를 통하여 제안된 방식의 효용성을 입증한다.

• Journal of Power Electronics
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• 제12권2호
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• pp.249-257
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• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.343-346
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• 2002

In recent, complex SVPWM (Space Vector PWM) algorithm can be easily implemented by high performance microprocessor and DSP. Various SVPWM techniques are widely studied due to the advantages of low harmonic distortion and high use ratio of D.C. link voltage. Most of various studies for improving of VS-PWM inverter performance are concentrated about switching pattern and zero pulse pattern split algorithms. However, dc link voltage that is determined at rated load and speed conditions is not proper in the low speed and under rated load. In this paper, analysis of current ripple with digitally implemented SVPWM inverter is introduced according to link voltage. The optimal link voltage in the designed inverter system and load condition is provided in order to suppress output voltage error and current ripple. As remaining the effective voltage vector interval per sampling period sufficiently, additional voltage error and current ripple are suppressed. The proposed algorithm is verified through digital simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2201-2208
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• 2014

In this research, the characteristics of Brush-less DC (BLDC) motor in accordance with winding connection method, both Y-connection and D -connection, has been identified with design methodology simply. BLDC motor has been designed for both winding connections, and their torque analysis has been performed considering ideal current source analysis and voltage source analysis with 6-step control. In addition, to reduce torque ripple of BLDC motor, caused by coil inductance, on voltage source analysis with 6-step control, we have proposed suitable control method which is Phase Advance Control. It is verified that the torque ripple has been decreased by virtue of phase advance control, advancing and widening conduction angle of switching, via performance analysis by Finite Element Analysis.