• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.48-54
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• 1999

We designed the optimal device parameters of the retrograde well and the gettering layer(buried layer) using the high energy ion implantation for the next generation of CMOS struoture and proposed two models and simulated these models with Athena and Atlas, Silvaco Co. We obtained trigger currents which is more than 600 ${\mu}A/{\mu}m$ when the structure has been combined the gettering layer and the retrograde well. And the second model(twin retrograde well) was obtained that holdingcurrents were over 2500${\mu}A/{\mu}m$. As results, the more heavier dose, the more improved the latch-up immunity. The n'-p' spacing was fixed a 2${\mu}m$ in both models.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.34-41
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• 1999

In this paper, hot carrier induced performance degradation of peripheral circuits in memory devices such as static type imput buffer, latch type imput buffer and sense amplifier circuit has been measured and analyzed. The used design and fabrication of the peripheral circuits were $0.8 {\mu}m$ standard CMOS process. The analysis method is to find out which device is most significantly degraded in test circuits by using spice simulation, and then to characterize the correlation between device and circuit performance degradation. From the result of the performance degradation of static type input buffer, the trip point was increased due to the transconductance degradation of NMOS. In the case of latch type input buffer, there was a time delay due to the transconductance degradation of NMOS device. Finally, hot carrier induced the decrease of half-Vcc voltage and the increased of sensing voltage in sense amplifier circuits have been measured.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.20-26
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• 1999

A CMOS 6-bit 100MSPS ADC for DBS receiver is designed. The proposed ADC is composed of folding block, latch block, and digital block. The cascode interpolating block and kickback reduced latch are proposed with a high speed architecture. To verify the performance of ADC, simulations are carried out by HSPICE. The ADC achieves a clock frequency of 100MHz with a power dissipation of 40mW for 3 V supply voltage. The active chip area is $1500{\mu}m{\times}1000{\mu}m$with $0.65{\mu}m$ 2-poly 2-metal CMOS process. Further, INL and DNL are within ${\pm}0.6LSB$, ${\pm}0.5LSB$, respectively. SNDR is about 33dB at 10MHz input frequency.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.1
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• pp.66-73
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• 2021

In this paper, we analyzed and considered the precision of parts produced by 3D printing methods. For the latch systems applied to the Wingline folding doors, the 3D shape of the door hinge part was printed using FDM and DLP methods. Then, the 3D printed shape was scanned to measure the dimensions and dimensional changes of the actual model. In the comparison and analysis of the 3D printed door hinge parts, because the output filling density is 100% owing to the characteristics of DLP 3D printing, the filling density in FDM 3D printing was also set to 100%.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.609-612
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• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.85-90
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• 2013

In this paper, 6bit SAR ADC tolerant to ionizing radiation is presented. Radiation tolerance is achieved by using the Dummy Gate Assisted (DGA) MOSFET which was proposed to suppress the leakage current induced by ionizing radiation and its comparing sample is designed with the conventional MOSFET. The designed ADC consists of binary capacitor DAC, dynamic latch comparator, and digital logic and was fabricated using a standard 0.35um CMOS process. Irradiation was performed by Co-60 gamma ray. After the irradiation, ADC designed with the conventional MOSFET did not operate properly. On the contrary, ADC designed with the DGA MOSFET showed a little parametric degradation of which DNL was increased from 0.7LSB to 2.0LSB and INL was increased from 1.8LSB to 3.2LSB. In spite of its parametric degradation, analog to digital conversion in the ADC with DGA MOSFET was found to be possible.

• Design & Manufacturing
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• v.17 no.3
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• pp.15-20
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• 2023

In the fine blanking process, which is a press operation known for producing parts with narrow clearances and high precision through the application of high pressure, die roll often occurs during the shearing process when the punch penetrates the material. This die roll phenomenon can significantly reduce the functional surface of the parts, leading to decreased product performance, strength, and fatigue life. In this research, we conducted an in-depth analysis of the factors influencing die roll in the curvature area of the fine blanking process and identified its root causes. Subsequently, we designed and experimentally verified a die roll reduction process specifically tailored for the door latch manufacturing process. Our findings indicate that die roll tends to increase as the curvature radius decreases, primarily due to the heightened bending moment resulting from reduced shape width-length. Additionally, die roll is triggered by the absorption of initial punch energy by scrap material during the early shearing phase, resulting in lower speed compared to the product area. To mitigate the occurrence of die roll, we strategically selected the Shaving process and carefully determined the shaving direction and clearance area length. Our experiments demonstrated a promising trend of up to 75% reduction in die roll when applying the Shaving process in the opposite direction of pre-cutting, with the minimum die roll observed at a clearance area length of 0.2 mm. Furthermore, we successfully implemented this approach in the production of door latch products, confirming a significant reduction in die roll. This research contributes valuable insights and practical solutions for addressing die roll issues in fine blanking processes.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.1
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• pp.23-33
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• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.230-234
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• 1996

A new trenched Hybrid Schottky INjection Field Effect Transistor (HSINFET) is proposed and verified by 2-D semiconductor device simulation. The feature of the proposed structure is that the hybrid Schottky injector is implemented at the trench sidewall and p-n junction injector at the upper sidewall and bottom of a trench. Two-dimensional simulation has been performed to compare the new HSINFET with the SINFET, conventional HSINFET and lateral insulated gate bipolar transistor(LIGBT). The numerical results shows that the current handling capability of the proposed HSINFET is significantly increased without sacrificing turn-off characteristics. The proposed HSINFET exhibits higher latch-up current density and much faster switching speed than the lateral IGBT. The forward voltage drop of the proposed HSINFET is 0.4 V lower than that of the conventional HSINFET and the turn-off time of the trenched HSINFET is much smaller than that of LIGBT.