• 디지털산업정보학회논문지
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• 제5권4호
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• pp.169-177
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• 2009

In come cases, people differently respond on the same joke or thoughtless behavior - sometimes like it and laugh, another time feel annoyed or angry. This fact is explained that experiences which we had in the past are remembered by emotional memory, so they cause different responses. When people face similar situation or feel similar emotion, they evoke the emotion experienced in the past and the emotional memory affects current emotion. This paper suggested the mechanism of the emotional memory using SOM through the similarity between the emotional memory and SOM learning algorithm. It was assumed that the mechanism of the emotional memory has also the characteristics of association memory, long-term memory and short-term memory in its process of remembering emotional experience, which are known as the characteristics of the process of remembering factual experience. And then these characteristics were applied. The mechanism of the emotional memory designed like this was applied to toy hammer game and I measured the change in the power of toy hammer caused by differently responding on the same stimulus. The mechanism of the emotional memory suggest in above is expected to apply to the fields of game, robot engineering, because the mechanism can express various emotions on the same stimulus.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.410-410
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• 2013

Next-generation nonvolatile memory (NVM) has attracted increasing attention about emerging NVMs such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory and resistance random access memory (RRAM). Previous studies have demonstrated that RRAM is promising because of its excellent properties, including simple structure, high speed and high density integration. Many research groups have reported a lot of metal oxides as resistive materials like TiO2, NiO, SrTiO3 and ZnO [1]. Among them, the ZnO-based film is one of the most promising materials for RRAM because of its good switching characteristics, reliability and high transparency [2]. However, in many studies about ZnO-based RRAMs, there was a problem to get lower current level for reducing the operating power dissipation and improving the device reliability such an endurance and an retention time of memory devices. Thus in this paper, we investigated that highly reproducible bipolar resistive switching characteristics of W doped ZnO RRAM device and it showed low resistive switching current level and large ON/OFF ratio. This may be caused by the interdiffusion of the W atoms in the ZnO film, whch serves as dopants, and leakage current would rise resulting in the lowering of current level [3]. In this work, a ZnO film and W doped ZnO film were fabricated on a Si substrate using RF magnetron sputtering from ZnO and W targets at room temperature with Ar gas ambient, and compared their current levels. Compared with the conventional ZnO-based RRAM, the W doped ZnO ReRAM device shows the reduction of reset current from ~$10^{-6}$ A to ~$10^{-9}$ A and large ON/OFF ratio of ~$10^3$ along with self-rectifying characteristic as shown in Fig. 1. In addition, we observed good endurance of $10^3$ times and retention time of $10^4$ s in the W doped ZnO ReRAM device. With this advantageous characteristics, W doped ZnO thin film device is a promising candidates for CMOS compatible and high-density RRAM devices.

• 컴퓨터교육학회논문지
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• 제15권3호
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• pp.37-47
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• 2012

고등학교 정보 과목의 주요한 교육 목표는 컴퓨터 과학에 대한 올바른 지식 습득 및 활용을 통한 창의적인 문제 해결력 향상에 있다. 이러한 교육 목표를 달성하기 위해서는 무엇보다도 정보 교과서의 내용이 정확하고 적절해야 한다. 그러나 현재의 정보 교과서에는 주기억 장치와 가상 메모리 관련 내용 중 정확성이 결여된 설명이 포함되어 있다. 교과서는 주기억 장치를 RAM과 ROM으로 분류하고 있으며, 가상 메모리를 주기억 장치보다 큰 프로그램을 실행하기 위해 보조기억 장치의 일부를 주기억 장치로 사용하는 것으로 설명하고 있다. 본 연구에서는 미국 대부분의 대학에서 교재로 사용되고 있는 컴퓨터 전문 서적과의 비교 분석을 통하여 정보 교과서에 존재하는 오류의 원인을 분석하고 개선 방안을 제시하고자 하였다. 연구 결과, 주기억 장치의 종류로 ROM을 포함시키는 것은 적절하지 않다는 것을 메모리 계층 구조를 통하여 보여주었다. 가상 메모리는 프로그래머의 편의를 위해 시스템이 제공하는 기술로 이를 통해 운영체제는 프로그램의 실행에 필요한 부분만을 보조기억 장치로부터 주기억 장치에 적재한다. 현재의 컴퓨터 시스템에서는 가상메모리를 사용하는 장점으로 주기억 장치보다 큰 프로그램을 실행할 수 있다는 점보다 다수의 프로그램이 주기억 장치를 공유하여 멀티태스킹을 효과적으로 지원한다는 점이 부각되어야 한다. 또한 가상 메모리는 고등학생의 인지 발달 수준에서 이해하기에는 복잡하고 어려운 개념이기 때문에 고등학교 교육과정에서는 다루지 않는 것이 바람직하다고 제안하였다.

• ETRI Journal
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• 제36권5호
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.40-45
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• 2008

We developed small molecular organic nonvolatile $4F^2$ memory cells using metal layer evaporation followed by $O_2$ plasma oxidation. Our memory cells sandwich an upper ${\alpha}$-NPD layer, Al nanocrystals surrounded by $Al_2O_3$, and a bottom ${\alpha}$-NPD layer between top and bottom electrodes. Their nonvolatile memory characteristics are excellent: the $V_{th},\;V_p$ (program), $V_e$ (erase), memory margin ($I_{on}/I_{off}$), data retention time, and erase and program endurance were 2.6 V, 5.3 V, 8.5 V, ${\approx}1.5{\times}10^2,\;1{\times}10^5s$, and $1{\times}10^3$ cycles, respectively. They also demonstrated symmetrical current versus voltage characteristics and a reversible erase and program process, indicating potential for terabit-level nonvolatile memory.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.143-151
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• 2010

In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.357-358
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• 2013

The non-linear characteristics of ON states are important for the application to the high density cross-point memory industry because the sneak current in neighbor cells occurred during reading, erasing, and writing process. Kw of above 20 in ON states, which is the writing current @ Vwrite/the current @ 1/2Vwrite, was required in cross-point ReRAM memory industry. The high current density non-linear IV curve of ZnSe selector was shown and the ALD HfO2 switching device has the linear properties of ON states and the compliance current of 100 uA. To evaluate the performance of the selection device, we connected itto HfO2 switching device in series. The bottom electrode of the selection device was connected to the top electrode of the RRAM. All of the bias was applied with respect to the top electrode of the selection device, whereas the bottom electrode of the RRAM was grounded. In the cross-point application, 1/2Vwrite and -1/2Vwrite were applied to the word-line and bit-line, respectively, which were connected to the selected cell, and a zero bias was applied to the unselected word-lines and bit-lines. The current @ 1/2Vwrite of the unselected cells was blocked by the selection device, thus eliminating the sneak path and obtaining a writing voltage margin. Using this method, the writing voltage margin was analyzed on the basis of the memory size.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.436-439
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• 2011

휴대용 디지털 기기 보급의 확산되면서 휴대용 저장장치 수요가 급증하고 있으며, 디지털 카메라 및 캠코더에서는 대부분 SD 메모리 카드를 이용하고 있다. SD 메모리 카드는 일반적으로 플래시 메모리를 기반으로 사용자 데이터를 저장한 후 PC에 데이터를 복사하는 형태로 사용되고 있다. 본 논문에서는 플래시 메모리에 데이터를 저장하는 방식이 아닌, 네트워크를 통하여 사진 및 영상 데이터 저장을 할 수 있는 SD 메모리 카드를 제안한다. SD Slave IP를 통해서 들어오는 데이터 및 메모리 주소 값들을 플래시 메모리로 보내지 않고 네트워크 서버에 전달하여, 실시간으로 SD 메모리에 저장할 데이터를 안전하고 편리하게 저장할 수 있다.