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http://dx.doi.org/10.5573/JSTS.2010.10.2.143

Simulation and Modelling of the Write/Erase Kinetics and the Retention Time of Single Electron Memory at Room Temperature  

Boubaker, Aimen (Departement d'electronique Institut des Nanotechnologies de Lyon-INL, INSA-Lyon)
Sghaier, Nabil (Departement des sciences physiques, Faculte des Sciences de Monastir)
Souifi, Abdelkader (Departement d'electronique Institut des Nanotechnologies de Lyon-INL, INSA-Lyon)
Kalboussi, Adel (Departement des sciences physiques, Faculte des Sciences de Monastir)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.10, no.2, 2010 , pp. 143-151 More about this Journal
Abstract
In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.
Keywords
Single electron transistor; single electron memory; retention time; SET/SEM; SIMON;
Citations & Related Records

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