• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.55-59
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• 2015

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

• Korean Journal of Metals and Materials
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• v.46 no.9
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• pp.585-592
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• 2008

Flip-chip bonding using Cu-Sn mushroom bumps composed of Cu pillar and Sn cap was accomplished, and the contact resistance and the thermal cycling reliability of the Cu-Sn mushroom bump joints were compared with those of the Sn planar bump joints. With flip-chip process at a same bonding stress, both the Cu-Sn mushroom bump joints and the Sn planar bump joints exhibited an almost identical average contact resistance. With increasing a bonding stress from 32 MPa to 44MPa, the average contact resistances of the Cu-Sn mushroom bump joints and the Sn planar bump joints became reduced from $30m{\Omega}/bump$ to $25m{\Omega}/bump$ due to heavier plastic deformation of the bumps. The Cu-Sn mushroom bump joints exhibited a superior thermal cycling reliability to that of the Sn planar bump joints at a bonding stress of 32 MPa. While the contact resistance characteristics of the Cu-Sn mushroom bump joints were not deteriorated even after 1000 thermal cycles ranging between $-40^{\circ}C$ and $80^{\circ}C$, the contact resistance of the Sn planar bump joints substantially increased with thermal cycling.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.477-478
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• 2012

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.831-832
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• 2013

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.27-32
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• 2010

For the flip chip joints processed using Cu pillar bumps and Sn pads, thermal cycling and high temperature storage reliabilities were examined as a function of the Sn pad height. With increasing the height of the Sn pad, which composed of the flip chip joint, from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance of the flip chip joint decreased from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$. Even after thermal cycles of 1000 times ranging from $-45^{\circ}C$ to $125^{\circ}C$, the Cu pillar flip chip joints exhibited the contact resistance increment below 12% and the shear failure forces similar to those before the thermal cycling test. The contact resistance increment of the Cu pillar flip chip joints was maintained below 20% after 1000 hours storage at $125^{\circ}C$.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.841-842
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• 2013

• Journal of Welding and Joining
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• v.31 no.3
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• pp.4-10
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• 2013

In electronic industry, the trend of future electronics will be flexible, bendable, wearable electronics. Until now, there is few study on bonding technology and reliability of bonding joint between chip with micro solder bump and flexible substrate. In this study, we investigated joint properties of Si chip with eutectic Sn-58Bi solder bump on Cu pillar bump bonded on flexible substrate finished with ENIG by flip chip process. After flip chip bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test, thermal shock test, and bending test. After thermal shock test, we observed that crack initiated between $Cu_6Sn_5IMC$ and Sn-Bi solder and then propagated within Sn-Bi solder and/or interface between IMC and solder. On the other hands, We observed that fracture propated at interface between Ni3Sn4 IMC and solder and/or in solder matrix after bending test.

• Journal of the Korean institute of surface engineering
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• v.48 no.4
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• pp.131-135
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• 2015

We investigated the surface morphology and the change of Ag concentration for SnAg electrodeposits according to the current density using labmade and commercial plating solutions. The concentration of Ag in the SnAg electrodeposits decreased with increasing the current density. The Ag concentrations at the conditions of over $50mA/cm^2$ were below 3 wt% and the surface was relatively smooth. Cu pillar bump was fabricated by using SnAg electroplating, and it was reflowed at $240^{\circ}C$ for 90 sec. The cross-sectional microstructure was investigated by using EBSD measurement and it was found that the grain size of SnAg became smaller by increasing the number of reflow treatments.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.469-470
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• 2012