• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.469-470
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• 2012

• Journal of the Korean institute of surface engineering
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• v.48 no.4
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• pp.131-135
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• 2015

We investigated the surface morphology and the change of Ag concentration for SnAg electrodeposits according to the current density using labmade and commercial plating solutions. The concentration of Ag in the SnAg electrodeposits decreased with increasing the current density. The Ag concentrations at the conditions of over $50mA/cm^2$ were below 3 wt% and the surface was relatively smooth. Cu pillar bump was fabricated by using SnAg electroplating, and it was reflowed at $240^{\circ}C$ for 90 sec. The cross-sectional microstructure was investigated by using EBSD measurement and it was found that the grain size of SnAg became smaller by increasing the number of reflow treatments.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.98-104
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• 2023

The feasibility of an efficient process proposed for Cu-Cu flip-chip bonding was evaluated by forming a porous Cu layer on Cu pillar and conducting thermo-compression sinter-bonding after the infiltration of a reducing agent. The porous Cu layers on Cu pillars were manufactured through a three-step process of Zn plating-heat treatment-Zn selective etching. The average thickness of the formed porous Cu layer was approximately 2.3 ㎛. The flip-chip bonding was accomplished after infiltrating reducing solvent into porous Cu layer and pre-heating, and the layers were finally conducted into sintered joints through thermo-compression. With reduction behavior of Cu oxides and suppression of additional oxidation by the solvent, the porous Cu layer densified to thickness of approximately 1.1 ㎛ during the thermo-compression, and the Cu-Cu flip-chip bonding was eventually completed. As a result, a shear strength of approximately 11.2 MPa could be achieved after the bonding for 5 min under a pressure of 10 MPa at 300 ℃ in air. Because that was a result of partial bonding by only about 50% of the pillars, it was anticipated that a shear strength of 20 MPa or more could easily be obtained if all the pillars were induced to bond through process optimization.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.477-478
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.473-474
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.831-832
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• 2013

• Korean Journal of Metals and Materials
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• v.46 no.9
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• pp.585-592
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• 2008

Flip-chip bonding using Cu-Sn mushroom bumps composed of Cu pillar and Sn cap was accomplished, and the contact resistance and the thermal cycling reliability of the Cu-Sn mushroom bump joints were compared with those of the Sn planar bump joints. With flip-chip process at a same bonding stress, both the Cu-Sn mushroom bump joints and the Sn planar bump joints exhibited an almost identical average contact resistance. With increasing a bonding stress from 32 MPa to 44MPa, the average contact resistances of the Cu-Sn mushroom bump joints and the Sn planar bump joints became reduced from $30m{\Omega}/bump$ to $25m{\Omega}/bump$ due to heavier plastic deformation of the bumps. The Cu-Sn mushroom bump joints exhibited a superior thermal cycling reliability to that of the Sn planar bump joints at a bonding stress of 32 MPa. While the contact resistance characteristics of the Cu-Sn mushroom bump joints were not deteriorated even after 1000 thermal cycles ranging between $-40^{\circ}C$ and $80^{\circ}C$, the contact resistance of the Sn planar bump joints substantially increased with thermal cycling.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.31-31
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• 2015

본 연구는, TAB(Tape Automated Bonding)접속이나 Flip Chip 접속에 의한 패캐징을 실현시키기 위해, 실리콘 웨이퍼 표면에 구리 필러 및 주석 합금을 전기 도금법으로 형성하는 전기 접점용 범프에 관한 것이다. 본 연구에서는, 균일 범프 두께, 범프 표면의 균일화, 범프 내의 보이드 발생 문제 해결, 균일한 합금 조성 및 도금 속도의 고속화를 위해, Cu 도금액 및 Sn-Ag 도금액의 첨가제에 의한 표면 형상의 제어를 중심으로 그 성능에 대해 보고한다.

• Korean Journal of Metals and Materials
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• v.49 no.2
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• pp.180-186
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• 2011

Isothermal annealing and electromigration tests were performed at $125^{\circ}C$ and $125^{\circ}C$, $3.6{\times}10_4A/cm^2$ conditions, respectively, in order to compare the growth kinetics of the intermetallic compound (IMC) in the Cu/thin Sn/Cu bump. $Cu_6Sn_5$ and $Cu_3Sn$ formed at the Cu/thin Sn/Cu interfaces where most of the Sn phase transformed into the $Cu_6Sn_5$ phase. Only a few regions of Sn were not consumed and trapped between the transformed regions. The limited supply of Sn atoms and the continued proliferation of Cu atoms enhanced the formation of the $Cu_3Sn$ phase at the Cu pillar/$Cu_6Sn_5$ interface. The IMC thickness increased linearly with the square root of annealing time, and increased linearly with the current stressing time, which means that the current stressing accelerated the interfacial reaction. Abrupt changes in the IMC growth velocities at a specific testing time were closely related to the phase transition from $Cu_6Sn_5$ to $Cu_3Sn$ phases after complete consumption of the remaining Sn phase due to the limited amount of the Sn phase in the Cu/thin Sn/Cu bump, which implies that the relative thickness ratios of Cu and Sn significantly affect Cu-Sn IMC growth kinetics.