• 마이크로전자및패키징학회지
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• 제14권4호
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• pp.63-69
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• 2007

Cu 비아를 이용한 MEMS 센서의 스택 패키지용 interconnection 공정을 연구하였다. Ag 페이스트 막을 유리기판에 형성하고 관통 비아 홀이 형성된 Si 기판을 접착시켜 Ag 페이스트 막을 Cu 비아 형성용 전기도금 씨앗층으로 사용하였다. Ag 전기도금 씨앗층에 직류전류 모드로 $20mA/cm^2$와 $30mA/cm^2$의 전류밀도를 인가하여 Cu 비아 filling을 함으로써 직경 $200{\mu}m$, 깊이 $350{\mu}m$인 도금결함이 없는 Cu 비아를 형성하는 것이 가능하였다. Cu 비아가 형성된 Si 기판에 Ti/Cu/Ti metallization 및 배선라인 형성공정, Au 패드 도금공정, Sn 솔더범프 전기도금 및 리플로우 공정을 순차적으로 진행함으로써 Cu 비아를 이용한 MEMS 센서의 스택 패키지용 interconnection 공정을 이룰 수 있었다.

• Korean Chemical Engineering Research
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• 제52권1호
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• pp.26-39
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• 2014

전자 소자의 구리 금속 배선은 전해 도금을 포함한 다마신 공정을 통해 형성한다. 본 총설에서는 배선 형성을 위한 구리 전해 도금 및 수퍼필링 메카니즘에 대해 다루고자 한다. 수퍼필링 기술은 전해 도금의 전해질에 포함된 유기 첨가제의 영향에 의한 결과이며, 이는 유기 첨가제의 표면 덮임율을 조절하여 웨이퍼 위에 형성된 패턴의 바닥 면에서의 전해 도금 속도를 선택적으로 높임으로써 가능하다. 소자의 집적도를 높이기 위해 금속 배선의 크기는 계속적으로 감소하여 현재 그 폭이 수십 nm 수준으로 줄어들었다. 이러한 배선 폭의 감소는 구리 배선의 전기적 특성 감소, 신뢰성의 저하, 그리고 수퍼필링의 어려움 등 여러 가지 문제를 야기하고 있다. 본 총설에서는 상기 기술한 문제점을 해결하기 위해 구리의 미세 구조 개선을 위한 첨가제의 개발, 펄스 및 펄스-리벌스 전해 도금의 적용, 고 신뢰성 배선 형성을 위한 구리 기반 합금의 수퍼필링, 그리고 수퍼필링 특성 향상에 관한 다양한 연구를 소개한다.

• 한국재료학회지
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• 제24권4호
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.95-99
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• 2001

Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New humping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study

• 마이크로전자및패키징학회지
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• 제22권2호
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• pp.55-59
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• 2015

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

• 대한금속재료학회지
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• 제48권6호
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.345-349
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• 2005

300 mW-cm의 낮은 비저항을 갖는 카본-질소$\_$텅스텐 (W-C-N) 확산방지막을 원자층 증착법으로 제조하였으며, 반응기체로 $WF_6-N_2-CH_4$를 사용하였다. $N_2$ 및 $CH_4$ 반응기체를 주입 할 때는 고주파 펄스를 인가하여 플라즈마에 의한 반응물의 분리가 일어나도록 하였다. 다층금속배선에 사용하는 층간 절연층 (TEOS) 위에서 W-C-N 박막은 원자층 증착기구를 따르며, 10에서 100 사이클 동안 증착율이 0.2nm/cycles 로 일정한 값을 가진다. 또한 Cu 배선을 위한 확산방지막으로써 W-C-N 박막은 비정질 상을 가지며, $800^{\circ}C$에서 30분간 열처리해도 Cu의 확산을 충분히 방지할 수 있음을 확인하였다.

• ETRI Journal
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• 제35권6호
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.111-119
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• 2005

직경 $75{\mu}m$ 높이 $90{\mu}m$및 $150{\mu}m$ 피치의 Cu via를 통한 삼차원 배선구조를 갖는 스택 시편을 deep RIE를 이용한 via hole 형성공정 , 펄스-역펄스 전기도금법에 의한 Cu via filling 공정, CMP를 이용한 Si thinning 공정, photholithography, 금속박막 스퍼터링, 전기도금법에 의한 Cu/Sn 범프 형성공정 및 플립칩 공정을 이용하여 제작하였다. Cu via를 갖는 daisy chain 시편에서 측정한 접속범프 개수에 따른 daisy chain의 저항 그래프의 기울기로부터 Cu/Sn 범프 접속저항과 Cu via 저항을 구하는 것이 가능하였다. $270^{\circ}C$에서 2분간 유지하여 플립칩 본딩시 $100{\times}100{\mu}m$크기의 Cu/Sn 범프 접속저항은 6.7 m$\Omega$이었으며, 직경 $75 {\mu}m$, 높이 $90{\mu}m$인 Cu via의 저항은 2.3m$\Omega$이었다.

• Transactions on Electrical and Electronic Materials
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• 제14권6호
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• pp.304-307
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• 2013

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.