• The Journal of the Acoustical Society of Korea
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• v.41 no.5
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• pp.507-517
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• 2022

The PhotoAcoustic Microscopy (PAM) has been proved to be a useful tool for biological and medical applications due to its high spatial and contrast resolution. PAM is based on transmission of laser pulses and reception of PA signals. Since the strength of PA signals is generally low, not only are high-performance optical and acoustic modules required, but high-performance electronics for imaging are also particularly needed for high-quality PAM imaging. Most PAM systems are implemented with a combination of several pieces of equipment commercially available to receive, amplify, enhance, and digitize PA signals. To this end, PAM systems are inevitably bulky and not optimal because general purpose equipment is used. This paper reports a PA signal receiving system recently developed to attain the capability of improved Signal to Noise Ratio (SNR) and Contrast to Noise Ratio (CNR) of PAM images; the main module of this system is a low noise, wideband signal receiver that consists of two low-noise amplifiers, two variable gain amplifiers, analog filters, an Analog to Digital Converter (ADC), and control logic. From phantom imaging experiments, it was found that the developed system can improve SNR by 6.7 dB and CNR by 3 dB, compared to a combination of several pieces of commercially available equipment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.6
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• pp.853-861
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• 2018

This paper proposes the application of harmonic constraints to address the problems caused by abnormal voltage increases when electric railway vehicles are running. The AC line that supplies the train with power during operation is used to provide electricity of 25kV/60 Hz, but gradually the size and frequency of harmonics involved in the line are varied with the technological evolution of the railroad vehicle electrical equipment. An increase in heat losses due to the failure of the instrument transformer (PT), the main circuit device, which is a serious problem with the recent train safety operation, or to the main displacement voltage. When high frequency components are introduced through low frequency Transformers of the main circuit device, the high intensity of the components is caused by the high intensity of the core and the current flow of the parasitic core is increased, thus generating heat. To solve this problem, the recent adjustment of the sequence has applied artificial NOTCH OFF of the power converter. However, the method of receiving and controlling the OFF signal operates by interaction between the ground and the vehicle's devices, thus it is invalid in the event of failure, and an actual accident is occurring. Therefore, the harmonic currents were required to prevent possible flow of harmonics, and conducted a study to prevent accidental occurrence of train accidents and to verify feasibility of the device through the simulations of the train's experimental analysis and the simulations of the train for safe operation.

• Journal of Advanced Navigation Technology
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• v.28 no.3
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• pp.348-355
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• 2024

A current source capable of stably supplying current as a measurement medium is required in order to measure and test important facilities that require large-scale measurement current, such as a control element drive mechanism control system(CEDMCS), in case of dismantling a nuclear power plant. However, it can provides only voltage power as a source, not current, although direct voltage controlled constant current source is essential to test major equipment. That kind of source is not available to supply stable constant current regardless of load variation. It is just voltage supplier. Developing current source is not easy other than voltage source. Very large-scale current source up to ampere class more than such ten times of normal current is inevitable to test above mentioned equipment. So, we developed large-scale current source which is controlled by input DC voltage and supplies constant stable current to object equipment according to this requirement. We measured and tested nuclear power plant equipment using given real site data for a long time and afforded long period load test, and then proved its validity and verification. The developed invetion will be used future installed important equipment measuring and testing.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• The Korean Journal of Nuclear Medicine
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• v.34 no.1
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• pp.82-93
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• 2000

Purpose: We characterized the signals obtained from the components of a small gamma camera using Nal(Tl)-position sensitive photomultiplier tube (PSPMT) and optimized the parameters employed in the modules of the system. Materials and Methods: The small gamma camera system consists of a Nal(Tl) crystal ($60{\times}60{\times}6mm^3$) coupled with a Hamamatsu R3941 PSPMT, a resister chain circuit, preamplifiers, nuclear instrument modules (NIMs), an analog to digital converter and a personal computer for control and display. The PSPMT was read out using a resistive charge division circuit which multiplexes the 34 cross wire anode channels into 4 signals (X+, X-, Y+, Y -). Those signals were individually amplified by four preamplifiers and then, shaped and amplified by amplifiers. The signals were discriminated and digitized via triggering signal and used to localize the position of an event by applying the Anger logic. The gamma camera control and image display was performed by a program implemented using a graphic software. Results: The characteristics of signal and the parameters employed in each module of the system were presented. The intrinsic sensitivity of the system was approximately $8{\times}10^3$ counts/sec/${\mu}Ci$. The intrinsic energy resolution of the system was 18% FWHM at 140 keV. The spatial resolution obtained using a line-slit mask and $^{99m}Tc$ point source were, respectively, 2.2 and 2.3 mm FWHM in X and Y directions. Breast phantom containing $2{\sim}7mm$ diameter spheres was successfully imaged with a parallel hole collimator. The image displayed accurate size and activity distribution over the imaging field of view Conclusion: We proposed a simple method for development of a small gamma camera and presented the characteristics of the signals from the system and the optimized parameters used in the modules of the small gamma camera.

• Investigative Magnetic Resonance Imaging
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• v.8 no.1
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• pp.42-49
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• 2004

Purpose : The quantization noise in magnetic resonance imaging (MRI) systems is analyzed. The signal-to-quantization noise ratio (SQNR) in the reconstructed image is derived from the level of quantization in the signal in spatial frequency domain. Based on the derived formula, the SQNRs in various main magnetic fields with different receiver systems are evaluated. From the evaluation, the quantization noise could be a major noise source determining overall system signal-to-noise ratio (SNR) in high field MRI system. A few methods to reduce the quantization noise are suggested. Materials and methods : In Fourier imaging methods, spin density distribution is encoded by phase and frequency encoding gradients in such a way that it becomes a distribution in the spatial frequency domain. Thus the quantization noise in the spatial frequency domain is expressed in terms of the SQNR in the reconstructed image. The validity of the derived formula is confirmed by experiments and computer simulation. Results : Using the derived formula, the SQNRs in various main magnetic fields with various receiver systems are evaluated. Since the quantization noise is proportional to the signal amplitude, yet it cannot be reduced by simple signal averaging, it could be a serious problem in high field imaging. In many receiver systems employing analog-to-digital converters (ADC) of 16 bits/sample, the quantization noise could be a major noise source limiting overall system SNR, especially in a high field imaging. Conclusion : The field strength of MRI system keeps going higher for functional imaging and spectroscopy. In high field MRI system, signal amplitude becomes larger with more susceptibility effect and wider spectral separation. Since the quantization noise is proportional to the signal amplitude, if the conversion bits of the ADCs in the receiver system are not large enough, the increase of signal amplitude may not be fully utilized for the SNR enhancement due to the increase of the quantization noise. Evaluation of the SQNR for various systems using the formula shows that the quantization noise could be a major noise source limiting overall system SNR, especially in three dimensional imaging in a high field imaging. Oversampling and off-center sampling would be an alternative solution to reduce the quantization noise without replacement of the receiver system.

• Korean Journal of Agricultural Science
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• v.8 no.1
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• pp.90-96
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• 1981

To design more efficient agricultural machinery, the accurately measuring system among many other factors is essential. A light-beam oscillographic recorder is generally used in measuring dynamic strain but it is not compatible with the extremely high speed measuring system such as 1,000 m/s, also is susceptable to damage due to vibration while using the system in field. The recorder used light sensitive paper for strip chart recording. The reading and analysis of data from the strip charts is very cumbersome, errorneous and time consuming. A microcomputer was interfaced with A/D converter, microcomputer program was developed for measuring, system calibration was done and the strain generated from a cantilever beam vibrator was measured. The results are summarized as follows. 1. Microcomputer program was developed to perform strain measuring of agricultural machine elements and could be controled freely the measuring intervals, no. of channels and no. of data. The maximum measuring speed was $62{\mu}s$. 2. Calibration the system was performed with triangle wave generated from a function generator and checked by an oscilloscope. The sampled data were processed using HP 3000 minicomputer of Chungnam National University computer center the graphical results were triangle same as input wave and so the system have been out of phase distorsion and amplitude distorsion. 3. The strain generated from a cantilever beam vibrator which has free vibration period of 0.019 second were measured by the system controlled to have l.0 ms of time interval and its computer output showing vibration curve which is well filted to theoretical value. 4. Using microcomputer on measuring the strain of agricultural machine elements could not only save analyzing time and recording papers but also get excellent adaptation to field experiment, especially in measurement requiring high speed and good precision.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.