• 한국ITS학회 논문지
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• 제11권4호
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• pp.63-69
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• 2012

본 논문에서는 용량성 지문센서의 회색조 이미지를 얻기 위한 새로운 회로를 제안하고 있다. 기존의 회로는 회색조 이미지를 얻기 위해 많은 칩 면적을 차지하는 DAC를 적용하거나 전력소모가 많고 전역 클럭을 적용하는 비휘발성 메모리에 적용되는 승압회로를 픽셀별로 적용하였다. 개선된 전하분할 방식의 용량성 지문센서 감지회로는 뉴런모스(vMOS) 기반의 DLC(down literal circuit) 회로와 단순화된 아날로그 MUX(multiplexor)를 적용하였다. 설계된 감지회로는 0.3V, $0.35{\mu}m$ CMOS공정을 적용하여 동작을 검증하였다. 제안된 회로는 기존의 비교기와 주변회로를 필요로하지 않으므로 단위 픽셀의 레이아웃 면적을 줄이고 이미지의 해상도를 향상 시킬 수 있다.

• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• 한국통신학회논문지
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• 제17권1호
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• pp.38-46
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• 1992

본 논문에서, 63_88MHz 밴드폭에서 25MHz 채널 스페이싱을 갖는 1023 채널과 100 hops/sec 호핑율을 가진 주파수 호핑 송수신기에 적용할 수 있는 고속 동기 회로를 수행했다. 동기과정(초기 동기와 트래킹)은 두 스텝으로 구성된다. Short hopping frequencies, synchronization prefix에 정합된 두개의 채널 수동 correlators를 사용한 변황된 정합 필터는 초기동기를 위해 제시되었다. 초기 동기의 확률을 증가 시키기 위해 prefix는 반복적으로 전송된다. correlator의 출력은 동기 결정회로로 보내지고 코드 시작 시간은 동기 결정회로에 대해서 알아낸다. 변형된 정합 필터 방법은 하드웨어의 복잡성을 줄이고 코드 획득을 빠르게 얻는 것은 가능하게 했다. 쿨럭 회복 회로는 tracking을 위해 PN코드를 발생했다.

• 전자공학회논문지B
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• 제29B권11호
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• 한국정보통신학회논문지
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• 제5권6호
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• pp.1175-1183
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• 2001

본 연구에서는 간단한 전자회로로 카오스 특성을 나타내는 Chua 회로 대신 더욱 유연성이 있는 SC-CNN(State-Controlled CNN)을 이용해서 2-double scroll 과 3-double scroll 회로를 구성하고 이를 이용 하여 하이퍼카오스 회로를 제작하였다. 제작된 하이퍼카오스 회로로 두 개 이상의 카오스 어트렉터가 약한 결합을 하는 과정에서 발생하는 위상차를 이용하여 동기화를 이루고, 동기화된 하이피카오스 신호에 정보신호를 합성하여 전송한 후 수신부에서 이를 복조하는 하이퍼카오스 비밀통신을 수행하였다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권4호
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• pp.174-179
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• 2002

In this paper, the modified simulation algorithms of the Auto Transformer (AT) feeding electric train system were proposed. To obtain terminal voltage of train by using equivalent circuit or the AT feeding system, the iterative method is proposed for which determine the train voltages. The train voltages are iteratively calculated from the system voltage drop and line impedance. In the carte study, the proposed method is verified from actual operation data of the Kwa-Chon line. Also it is verified that the proposed method can be extent to the multi-train simulation tool. The terminal voltage of the multi-train can be calculated by using superposition principle and it is easily applied to the proposed method. Therefore, the proposed method can be a solution for the complexity of the circuit analysis in the existing methods.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.55-57
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• 1997

This paper develops the advanced method for the calculation of the equivalent circuit parameters of induction motor. An Induction motor is magnetically coupled system. But the conventional motor (the permeance method) calculates the each component of parameters separately. And it highly depends on the experimental factors and experiences to compensate the errors due to the some assumptions. Rut the proposed method calculates the parameters fully from the results of 2 dimensional finite element analysis. So the complexity in geometry and the non linearity of induction motor can be considered. And the computational cost is reduced compared with the conventional field and circuit approach. The results are compared with parameters from the permeance method. And it is verified by the comparison with the experimental results.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권4호
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• pp.200-207
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• 2004

This paper presents a simple and fast delay metric RC-class interconnects under saturated ramp inputs. The RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from delay metric under step input easily As compared with similar techniques proposed in previous researches, it is shown that the FDM technique complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권1호
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• ETRI Journal
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• 제43권4호
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.