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An Analytic Study on Estimating Delay Time in RC-class Interconnects Under Saturated Ramp Inputs  

김기영 (숭실대학 컴퓨터학과)
김승용 (숭실대학 컴퓨터학과)
김석윤 (숭실대학 컴퓨터학과)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers C / v.53, no.4, 2004 , pp. 200-207 More about this Journal
Abstract
This paper presents a simple and fast delay metric RC-class interconnects under saturated ramp inputs. The RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from delay metric under step input easily As compared with similar techniques proposed in previous researches, it is shown that the FDM technique complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.
Keywords
Interconnects; delay metric; timing; ramp, fast analysis;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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1 RICE: Rapid interconnect circuit evaluator /
[ C.L.Ratzlaff;N.Gopal;L.T.Pillage ] / Proc. IEEE/ACM Design Automation Conf.
2 M. T. Abuelma'atti, 'The Waveform Degradation in VLSI Interconnections,' IEEE J. Solid-State Circuits 25, Aug. 1990, pp. 1014-1016   DOI   ScienceOn
3 N. Menezes, S. Pullela, F. Dartu, and L. T. Pillage, 'RC Interconnect Synthesis - A Moment Fitting Approach,' Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1994, pp. 418-425
4 C. V. Kashyap, C. J. Alpert, Frank Liu, and A. Devgan, 'Closed Form Expressions for Extending Step Delay and Slew Metrics to Ramp Imputs,' ACM/SIGDA 2003 International Symposium on Physical Design(ISPD'03), April. 2003   DOI
5 The AS/X User's Guide, IBM Crop., 1996
6 L. Nagel, 'SPICE2, A computer program to simulate semiconductor circuits,' Univ. California, Berkeley, CA, TR ERL-M520, May 1995
7 H. R. Kaupp, 'Waveform Degradation in VLSI Interconnections,' IEEE J. Solid-State Circuits 24, Aug. 1989, pp. 1150-1153   DOI   ScienceOn
8 A. B. Kahng and S. Muddu, 'Analysis of RC Interconnections Under Ramp Input', UCLA CS Dept. TR-960013, April. 2003
9 김석윤, VLSI 시스템 회로 연결선의 모형화 및 해석, IDEC 교재개발시리즈 10, 시그마 프레스, 1999
10 W. C. Elmore, 'The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,' Journal of Applied Physics 19, Jan. 1948   DOI
11 Jessica Qian, Satyamurthy Pullela, and Lawrence T. Pillage, 'Modeling the Effective Capacitance for the RC Interconnect of CMOS Gates,'IEEE Trans. on Computer-Aided Design of Integrated Circuits and System, vol. 13, no. 12, Dec. 1994   DOI   ScienceOn
12 L. T. Pillage and R. A. Rohrer, 'Asymptotic Waveform Evaluation for Timing Analysis,' IEEE Trans. on CAD 9, Apr. 1990   DOI   ScienceOn
13 A. B. Kahng and S. Muddu, 'Accurate analytical delay models for VLSI interconnects,' Univ. California, Los Angeles, CA, UCLA CS Dept. TR-950034, Sept. 1995
14 A. B. Kahng and S. Muddu, 'An analytical delay model for RLC interconnects,' IEEE Trans. Computer-Aided Design, vol. 16, pp. 1507-1514, Dec. 1997   DOI   ScienceOn
15 B. Tutuianu, F. Dartu and L. T. Pileggi, 'Explicit RC-circuit delay approximation based on the first three moments of the impulse response,' in Proc. IEEE/ACM Design Automation Conf., June 1996, pp.611-616
16 R. Kay and L. T. Pileggi, 'PRIMO: Probability interpretation of moments for delay calculation,' Proc. IEEE/ACM Design Automation Conference, June 1998, pp.463-468
17 T. Lin, E. Acar, and L. T. Pileggi, 'h-gamma: An RC delay metric based on a gamma distribution approximation to the homogeneous response,' in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1998, pp.19-25
18 C. J. Alpert, A, Devgan, and C. Kashyap, 'RC Delay Metrics for Performance Optimization,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp.571-582, May 2001   DOI   ScienceOn
19 P. R. O'Brien and T. L. Savarino, 'Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation,' Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1989, pp. 512-515   DOI
20 A. B. Kahng and S. Muddu, 'Efficient Gate Delay Modeling for Large Interconnect Loads,' IEEE Multi-Chip Module Conf., Feb. 1996   DOI
21 R. Gupta, Bogdan Tutuianu and Lawrence T. Pileggi, 'The Elmore Delay as a Bound for RC Trees with Generalized Input Signals,' ACM/IEEE Design Automation Conference, June 1995, pp. 364-369   DOI
22 C. L. Ratzlaff, N. Gopal, and L. T. Pillage, 'RICE: Rapid interconnect circuit evaluator,' Proc. IEEE/ACM Design Automation Conf., June 1991, pp. 555-560
23 J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, 'Signal delay in RC tree networks,' IEEE Trans. on Computer Aided Design, vol. 2, pp.202-211, 1983   DOI   ScienceOn
24 김승용, 김기영, 김석윤, 'RC-class 연결선의 축소모형을 이용한 대수적 지연시간 계산법', KIEE Trans., Vol. 52C, No. 5, May. 2003
25 Qinwei Xu and Pinaki Mazumder, 'Efficient Macromodeling for On-chip Interconnects,' Proceedings of ASP-DAC, 2002   DOI