• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.633-643
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• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.74-82
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• 2015

As the complexity of an electronic device and the reduction of its operating voltage is progressing, susceptibility test of the chip and module for internal or external noises is essential. Although the immunity compliance of the chip was served with IEC 62132-4 Direct Power Injection method as an industry standard, in fact, EM immunity of the chip is influenced by their Power Domain Network (PDN). This paper evaluates the EM noise tolerance of a PLL and compares their noise transfer characteristics to the PLL on various PCB boards. To make differences of the PDNs of PCBs, various PCBs with or without LDO and with several types of capacitors are tested. For evaluation of discrepancies between EM characteristics of an IC only and the IC on real boards, the analysis of the noise transfer characteristics according to the PDNs shows that it gives important information for the design having robust EM characteristics. DPI measurement results show that greatly improved immunity of the PLL in the low-frequency region according to using the LDO and a frequency change of the PLL according to the DPI could also check with TEM cell measurement spectrum.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.15-22
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• 2004

This paper presents the channel analysis considering power distribution network(PDN) system of PCB. For achieve the target PDN system we proposed the useful design approach for acquiring the characteristic target of power distribution network in overall frequency ranges. The proposed method is based on the hierarchical approach related to frequency ranges and the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors and the board through it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. The analysis of PDN system shows that although the effective inductance of package dominatly affects the power noise and the signal transfer through data channel, the board PDNs also can not be neglected for achieving the accurate channel signaling. Therefore, we must design concurrently the chip, package, and board from the initial spec design of high speed digital system.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.