Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Layout-Based Inductance Model for On-Chip Power Distribution Grid Structures

레이아웃 기반 온-칩 전력 분배 격자 구조의 인덕턴스 모델 개발 및 적용

  • Jo, JeongMin (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 조정민 (성균관대학교 정보통신공학대학) ;
  • 김소영 (성균관대학교 정보통신공학대학)
  • Received : 2012.05.16
  • Published : 2012.09.25
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Abstract

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

Keywords

References

  1. R. Jakushokas, and E.G. Friedman, "Multi-Layer Interdigitated Power Distribution Networks", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, May 2011.
  2. 김소영, "Interconnect Scaling에 따른 온칩 인터커넥 인덕턴스의 중요성 예측," 전자공학회 논문지, 제48권 SD편, 제3호, 164-172쪽, 2011년 3월.
  3. R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Kose, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors. New York: Springer-Verlag, Second Edition, 2011.
  4. A. Muramatsu, M. Gachmoto, H. Onodera, "Effects of On-chip Inductance on Power Distribution Grid," IEICE Trans. Fundamentals, vol. e88-A, no. 12, Dec. 2005.
  5. K.Gala, D. Blaauw, V. Zolotov, P. M. Vaidya. and Anil Joshi, "Inductance Model and Analysis Methodology for High-Speed On-Chip Interconnect", IEEE Trans. on VLSI Systems, Vol. 10, No. 6, Dec. 2002.
  6. So Young Kim, Y. Massoud, S. S. Wong, "On the accuracy of return path assumption for loop inductance extraction for loop inductance extaction for 0.1um technology and beyond", Quality Electronic Design, 2003, 24-26 March 2003, pp. 401-404.
  7. 이상민, 문규, 위재경, "파워 분배망을 고려한 디지털 회로 시스템의 설계와 분석", 전자공학회 논문지, 제 41권 SD편, 제4호, 15-21쪽, 2004년 4월.
  8. Sang-Pil Sim, C. Chao, S. Krishnan, D. M. Petranovic, N. D. Arora, and Kwyro Lee, "An Effective Loop Inductance Model for General Non-Orthogonal Interconnect with Random Capacitive Coupling", Electron Devices Meeting, pp. 315-318, Dec. 2002.
  9. R. Jakushokas and Eby G. Friedman, "Inductance Model of Interdigitated Power and Ground Distribution Networks", IEEE Transaction on Circuits and Systems. II: Express Briefs, Vol. 56, No. 7, pp. 585-589, July 2009. https://doi.org/10.1109/TCSII.2009.2023297
  10. http://www.mentor.com.
  11. Xiaoning Qi, Gaofeng Wang, Zhiping Yu, R. W. Dutton, Tak Young, N. Chang, "On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation," Custom Integrated Circuits Conference, 2000, pp.487-490.
  12. 류순걸, 어영선, 심종인, "고속/고밀도 VLSI 회로 의 공진현상을 감소시키기 위한 효율적인 파워/그 라운드 네트워크 설계", 전자공학회 논문지, 제43 권 SD편, 제7호, 29-37쪽, 2006년 7월.
  13. N. Delorme, M. Belleville, J. Chilo, "Inductance and Capacitance Analytic Formulas for VLSI Interconnects," Electronic Letters, 23rd, vol. 32, no. 11, May 1996.
  14. http://www.ti.com/lit/an/snoa405a/snoa405a.pdf, Application Note 1205 Electrical Performance of Packages, Texas Instruments.