• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.209-212
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• 2000

Charge pump based upon a phase locked loop(PLL) is described. This charge pump show that it is possible to overcome the issue of charge pump current mismatch by using a current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. HSPICE simulations are performed using 0.25$\mu\textrm{m}$ CMOS process.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• Journal of Advanced Marine Engineering and Technology
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• v.31 no.5
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• pp.558-566
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• 2007

The performance characteristics of water-chilling heat pump using $CO_2$ with respect to variation of refrigerant charge amount was investigated experimentally. An experimental apparatus is consisted of a compressor, a gas cooler, an expansion valve, an evaporator and a liquid receiver. All heat exchangers used in the test rig are counter-flow-type heat exchangers with concentric dual tubes, which are made of copper. The gas cooler and the evaporator consist of 6 and 4 straight sections respectively arranged in parallel, each has 2400 mm length. The experimental results summarize as the followings : As the refrigerant charge ratio of $CO_2$ heat pump system increases, the discharge pressure and compressor ratio increases, but mass flow rate of refrigerant decreases. Also the compressor work increases with the increase of refrigerant charge ratio. However, the heating and cooling capacity of $CO_2$ heat pump decreases as the refrigerant charge ratio increases. The maximum heating COP of $CO_2$ heat pump system presented at 0.25 refrigerant charge ratio. It is possible to confirm the optimum charge ratio of $CO_2$ heat pump system by the viewpoint of heating COP.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.37-42
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• 2012

In this paper, a new charge pump is proposed to reduce the timing mismatch in the conventional current-steering charge pumps. Conventional current-steering charge pumps used NMOS input stages both for UP and DOWN signals, which resulted in different numbers of stage for UP and DOWN delay paths. The proposed charge pump has equalized the numbers of stages for UP and DOWN signals by using a PMOS stage for the DOWN signal. The simulation results show that the conventional current-steering charge pump has 14ns and 6ns for optimized timing mismatches between UP and DOWN signals for turn-on and turn-off, respectively. On the other hand, the proposed charge pump has improved timing mismatches of 6ns and 5ns for turn-on and turn-off, respectively. As a result, the reference spurs are reduced from -26dBc to -39dBc for the proposed charge pump. The proposed charge pump was designed by using $0.18{\mu}m$ CMOS technology. The measurement results show that the maximum variation of the charging and discharging current over the charge pump output voltage range of 0.3~1.5V is approximately 1.5%.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.353-359
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• 2012

A highly efficient charge pump that minimizes the reverse charge sharing current (in short, reverse current) is proposed. The charge pump employs auxiliary capacitors and diode-connected MOSFET along with an early clock to drive the charge transfer switches; this new method provides better isolation between stages. As a result, the amount of reverse current is reduced greatly and the clock driver can be designed with reduced transition slope. As a proof of the concept, a 1.1V-to-9.8 V charge pump was designed in a $0.35{\mu}m$ 18 V CMOS technology. The proposed architecture shows 1.6 V ~ 3.5 V higher output voltage compared with the previously reported architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.44-47
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• 2008

In this paper, a new circuit is proposed to minimize the charging and discharging current mismatch in charge pump for UWB PLL application. By adding a common-gate and a common-source amplifier and building the feedback voltage regulator, the high driving charge pump currents are accomplished. The proposed circuit has a wide operation voltage range, which ensures its good performance under the low power supply. The circuit has been implemented in an IBM 0.13um CMOS technology with 1.2V power supply. To evaluate the design effectiveness, some comparisons have been conducted against other circuits in the literature.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.386-393
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• 2007

Charge-pump high voltage inverter for Plasma backlight using CIM(Current Injection Method) is proposed in this paper. Adoption of ERC(Energy Recovery Circuit) is a new attempt in high voltage inverter so that it is not only energy recovery but also improvement of discharge stability and system unstability which is interrupted by noise. Using a charge-pump technique enables low voltage switches to be usable, the cost can be reduced. CIM is adopted to achieve high speed energy recovery in proposed circuit. Operations of the proposed circuit are analyzed for each mode. The proposed circuit is verified to be applicable on a 32 inch plasma backlight panel by experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.137-145
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• 2008

In this paper, novel CMOS charge pump having NMOS and PMOS transfer switches and a bulk-pumping circuit has been proposed. The NMOS and PMOS transfer switches allow the charge pump to improve the current-driving capability at the output. The bulk-pumping circuit effectively solves the bulk forward problem of the charge pump. To verify the effectiveness, the proposed charge pump was designed using a 80-nm CMOS process. The comparison results indicate that the proposed charge pump enhances the current-driving capability by more than 47% with pumping speed improved by 9%, as compared to conventional charge pumps having either NMOS or PMOS transfer switch. They also indicate that the charge pump reduces the worst-case forward bias of p-type bulk by more than 24%, effectively solving the forward current problem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1741-1746
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• 2012

This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generates about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.