• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.683-685
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• 2012

This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.9
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• pp.21-30
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• 1999

Halo pocket implantation in MOSFETs, which is known to be an efficient method to provent the punchthrough and threshold voltage roll-off phenomena, decreases the drain current of MOSFET devices. Although the decrease of the drain current in halo structure MOSFET is usually explained in terms of the increase of the threshold voltage, more decrease in the drain current than is predicted by the increased threshold voltage has experimentally been observed. In this work, the effect of halo doping profile on the drain current degradation is investigated in terms of the field distribution along the channel. Effective mobility model of the halo MOSFETs due to pocket implantation is presented and the degradation of the mobility is shown to be effective in the further decrease of the drain current. Present model is shown to be in good agreement with experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.799-804
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• 2016

To analyze the phenomenon of drain induced barrier lowering(DIBL) for top and bottom gate oxide thickness of asymmetric double gate MOSFET, the deviation of threshold voltage is investigated for drain voltage to have an effect on barrier height. The asymmetric double gate MOSFET has the characteristic to be able to fabricate differently top and bottom gate oxide thickness. DIBL is, therefore, analyzed for the change of top and bottom gate oxide thickness in this study, using the analytical potential distribution derived from Poisson equation. As a results, DIBL is greatly influenced by top and bottom gate oxide thickness. DIBL is linearly decreased in case top and bottom gate oxide thickness become smaller. The relation of channel length and DIBL is nonlinear. Top gate oxide thickness more influenced on DIBL than bottom gate oxide thickness in the case of high doping concentration in channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.431-431
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• 2011

Graphene, two dimensional sheet of sp2-hybridized carbon, has attracted an enormous amount of interest due to excellent electrical, chemical and mechanical properties for the application of transparent conducting films, clean energy devices, field-effect transistors, optoelectronic devices and chemical sensors. Especially, graphene is promising candidate to detect the gas molecules and biomolecules due to the large specific surface area and signal-to-noise ratios. Despite of importance to the disease diagnosis, there are a few reports to demonstrate the graphene- and rGO-FET for biological sensors and the sensing mechanism are not fully understood. Here we describe scalable and facile fabrication of rGO-FET with the capability of label-free, ultrasensitive electrical detection of a cancer biomarker, prostate specific antigen/${\alpha}1$-antichymotrypsin (PSA-ACT) complex, in which the ultrathin rGO sensing channel was simply formed by a uniform self-assembly of two-dimensional rGO nanosheets on aminated pattern generated by inkjet printing. Sensing characteristics of rGO-FET immunosensor showed the highly precise, reliable, and linear shift in the Dirac point with the analyte concentration of PSA-ACT complex and extremely low detection limit as low as 1 fg/ml. We further analyzed the charge doping mechanism, which is the change in the charge carrier in the rGO channel varying by the concentration of biomolecules. Amenability of solution-based scalable fabrication and extremely high performance may enable rGO-FET device as a versatile multiplexed diagnostic biosensor for disease biomarkers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.1-7
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• 2011

In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.11-11
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• 2007

1차원 구조체인 반도체 나노선은 앙자제한효과 (quantum confinement effect) 등을 이용하여 고밀도/고효율의 소자 개발이 기대되고 있다. GaN는 상온에서 3.4 eV의 밴드갭 에너지를 갖는 III-V 족 반도체 재료로써 박막의 경우 광전자 소자로 폭넓게 응용되고 있다. 최근 GaN 나노선의 합성에 성공하면서 발광소자, 고효율의 태양전지, HEMT 등으로의 응용을 위한 많은 연구가 활발히 이루어지고 있다. 하지만, 아직까지 GaN 나노선의 전기적 특성을 제어하는 기술은 확립되지 않고 있다. 본 연구에서는 Vapor solid (VS)법을 이용하여 GaN 나노선을 합성하였으며, GaN 분말과 함께 $Mg_2N_3$ 분말을 첨가하여 (Ga,Mg)N 나노선을 성공적으로 합성하였다. 합성시에 GaN와 Mg 소스간의 거리 변화를 통해 Mg 도핑농도를 제어하고자 하였다. 이 같은 방법으로 합 된 (Ga,Mg)N 나노선의 Mg 도핑농도에 따른 결정학적 특성을 알아보고, (Ga,Mg)N 나노선을 이용하여 소자를 제작한 후 그 전기적 특성을 살펴보고자 한다. X-ray diffraction (XRD)과 high-resolution transmission electron microscopy (HRTEM), EDX를 이용하여 합성된 나노선의 결정학적 특성과 Mg의 도핑 농도를 확인하였다. Photo lithography와 e-beam lithography법을 이용하여 (Ga,Mg)N 나노선 field-effect transistor (FET)를 제작하고, channel current-drain voltage ($I_{ds}-V_{ds}$) 와 channel current-gate voltage ($I_{ds}-V_g$) 측정을 통해 (Ga,Mg)N 나노선이 도핑 농도에 따라 n형에서 p형으로 전기적 특성이 변화함을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.709-712
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• 2008

본 연구에서는 이중게이트 MOSFET 제작시 가장 중요한 요소인 채널도핑농도가 전송특성에 미치는 영향을 분석하고자 한다. 이를 위하여 분석학적 전송모델을 사용하였으며 분석학적 모델을 유도하기 위하여 포아슨방정식을 이용하였다. 나노구조 이중게이트 MOSFET에서 문턱전압이하의 전류전도에 영향을 미치는 열 방사전류와 터널링전류에 대하여 분석하였으며 본 연구의 모델이 타당하다는 것을 입증하기 위하여 서브문턱스윙값과 채널도핑농도의 관계를 이차원 시뮬레이션 값과 비교하였다. 결과적으로 본 연구에서 제시한 전송특성모델이 이차원 시뮬레이션모델과 매우 잘 일치하였으며 이중게이트 MOSFET의 구조적 파라미터에 따라 전송특성을 분석하였다.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.833-837
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• 2012

This paper proposes a DRAM data retention time enhancement method that minimizes silicon loss and undercut at STI sidewall by reducing the SC1 (Standard Cleaning) time. SC1 time optimization debilitates the parasitic electric field in STI's top corner, which reduces an inverse narrow width effect to result in reduction of channel doping density without increasing the subthreshold leakage of cell Tr. Moreover, it minimizes the electric field in depletion area from cell junction to P-well, increasing yield or data retention time.