Browse > Article
http://dx.doi.org/10.13067/JKIECS.2012.7.4.833

Enhancement of Data Retention Time in DRAM through Optimization of Sidewall Oxidation Precleaning  

Chai, Yong-Yoong (계명대학교 전자공학과)
Yoon, Kwang-Yeol (계명대학교 전자공학과)
Publication Information
The Journal of the Korea institute of electronic communication sciences / v.7, no.4, 2012 , pp. 833-837 More about this Journal
Abstract
This paper proposes a DRAM data retention time enhancement method that minimizes silicon loss and undercut at STI sidewall by reducing the SC1 (Standard Cleaning) time. SC1 time optimization debilitates the parasitic electric field in STI's top corner, which reduces an inverse narrow width effect to result in reduction of channel doping density without increasing the subthreshold leakage of cell Tr. Moreover, it minimizes the electric field in depletion area from cell junction to P-well, increasing yield or data retention time.
Keywords
DRAM; Data Retention Time; sidewall oxidation; SC1; Yield; Silicon;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 T. Hammoto, S. sugiura, and S. Sawada, "On the retention time distribution of dynamic random access memory(DRAM)," IEEE Trans. Electron Devices, Vol. 45, pp. 1300-1309, June 1998.   DOI
2 A. Hiraiwa, M. Ogasawara, N. Natsuaki, Y.Itoh, and H. Iwai, "Local field enhancement model of DRAM retention failure," in IEDM Tech. Dig, pp. 157-160, 1998.
3 S. Ueno, T. Yamashita, H. Oda, S. Komori, Y. Inoue, and T. Nishimura, "Leakage current observation on irregular local PN junctions forming the tail distributionof DRAM retention characteristics, with new test structure," in IEDM Tech Dis, pp. 153-156, 1998.
4 N. Shigyo and T. Hiraoka, "A review of narrow channel effects for STI MOSFET's: Adifference between surface and buried channel cases," Solid State Electron, Vol. 43 pp. 2061-2066, 1999.   DOI
5 S. Matsuda, T. Sato, H. Yoshimura, Y. Takewara, A. Sudo, I. Mizushima, Y. Tsunashima, and Y. Toyoshima, "Novel corner rounding process for shallow trench isolation utilizing MSTS," in IDEM Tech. Dig, pp. 137-140, 1998.
6 정채용, "다단 인터리브드 부스트 컨버터의 입력리플전류 수식 분석," 한국전자통신학회논문지, 6권, 6호, pp. 865-871, Dec. 2011.
7 김성권, 이경량, 여성대, 홍순양, 박용운, "모니터링된 배터리 전압 변환을 위한 SAR typed A/D 컨버터의 제작," 한국전자통신학회논문지, 6권, 2호, pp. 256-261, April. 2011.
8 J. Lee, D. Ha, and K. Kim, "Novel Cell Transistor Using Retracted Si3N4-Liner STI for the Improvement of Data Retention Time in Gigabit Density DRAM and Beyond," IEEE Trans. Electron Devices, Vol. 48, pp. 1152-1157, June 2001.   DOI
9 김창복, Pipeline 방식을 이용한 고성능 ADC설계에 관한 연국, 한국 QA학회논문지, 제6권, 2호, pp. 101-107, July, 2001.
10 T. Lee, I. N. Hajj, E. M. Rudnick, J. H. Patel, "Genetic-algorithm based test generation for current testing of bridging faults in CMOS VLSI circuits," IEEE VLSI Test Symposium, pp. 456-462, 1996.
11 X. Wen, H. tamamoto and K. Kinoshita, "IDDQ Test Vector Selection for Transistor Short Fault Testing", System and Computers in Japan, Vol. 28, No. 5, 1997.