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Enhancement of Data Retention Time in DRAM through Optimization of Sidewall Oxidation Precleaning

측면산화 프리크리닝의 최소화를 통한 DRAM의 데이터 유지시간 개선

  • Received : 2012.06.07
  • Accepted : 2012.08.09
  • Published : 2012.08.31

Abstract

This paper proposes a DRAM data retention time enhancement method that minimizes silicon loss and undercut at STI sidewall by reducing the SC1 (Standard Cleaning) time. SC1 time optimization debilitates the parasitic electric field in STI's top corner, which reduces an inverse narrow width effect to result in reduction of channel doping density without increasing the subthreshold leakage of cell Tr. Moreover, it minimizes the electric field in depletion area from cell junction to P-well, increasing yield or data retention time.

SC1(Standard Cleaning) 시간을 줄여 STI 측벽에서의 실리콘 손실 및 과도절개를 최소화하여 DRAM에서의 데이터 유지시간을 증가시키는 방법을 제안한다. SC1 시간 최적화를 통해 STI 상층 모서리부에서의 기생 전기장을 약화시킴으로서 Inverse Narrow Width 효과를 감소시키면 셀 트랜지스터의 Subthreshold 누설의 증가없이 채널 도핑농도가 감소하게 된다. 이것은 셀 접합에서 P-Well간 공핍 영역에서의 전기장을 최소화하여 일드나 데이터 유지시간의 증가를 보여 주었다.

Keywords

References

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