• Journal of Information Display
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• v.6 no.2
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• pp.16-18
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.211.2-211.2
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• 2015

In order to investigate the effect of front channel in DAL (dual active layer) TFT (thin film transistor), we successfully fabricated DAL TFT composed of ITZO and IGZO as active layer using the solution process. In this structure, ITZO and IGZO active layer were used as front and back channel, respectively. The front channel was changed from 0.05 to 0.2 M at fixed 0.3 M IGZO of back channel. When the mol concentration of front channel was increased, the threshold voltage (VTH) was increased from 2.0 to -11.9 V and off current also was increased from 10-12 to 10-11. This phenomenon is due to increasing the carrier concentration by increasing the volume of the front channel. The saturation mobility of DAL TFT with 0.05, 0.1, and 0.2 M ITZO were 0.45, 4.3, and $0.65cm2/V{\cdot}s$. Even though 0.2 M ITZO has higher carrier concentration than 0.05 and 0.1 M ITZO, the 0.1 M ITZO/0.3 M IGZO DAL TFT has the highest saturation mobility. This is due to channel defect such as pores and pin-holes. These defect sites were created during deposition process by solvent evaporation. Due to these defect sites, the 0.1 M ITZO/0.3 M IGZO DAL TFT shows the higher saturation mobility than that of DAL TFT with front channel of 0.2 M ITZO.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.377-377
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• 2014

We demonstrate the high temperature-dependent electrical behavior at 2D multilayer MoS2 transistor. Our previous reports explain that the extracted field-effect mobility of good device was inversely proportional to the increase of temperature. Because scattering mechanism is dominated by phonon scattering at a well-designed MoS2 transistor, having, low Schottky barrier. However, mobility at an immature our $MoS_2$ transistor (${\mu}m$ < $10cm^2V^{-1}s^{-1}$) is proportional to the increase temperature. The existence of a big Schottky barrier at $MoS_2-Ti$ junction can reduce carrier transport and lead to lower transistor conductance. At high temperature (380K), the field-effect mobility of multilayer $MoS_2$ transistor increases from 8.93 to $16.9cm^2V^{-1}sec^{-1}$, which is 2 times higher than the value at room temperature. These results demonstrate that carrier transport at an immature $MoS_2$ with a high Schottky barrier is mainly affected by thermionic emission over the energy barrier at high temperature.

• Journal of Advanced Marine Engineering and Technology
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• v.24 no.6
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• pp.61-69
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• 2000

Indium-Tin Oxide (ITO) films were prepared on the commercial glass substrate by the Magnetron Sputtering method. The target was a 90wt.% $In_2O_3$-10wt.% $SnO_2$with 99.99% purity. The ITO films deposited by changing the partial pressure of oxygen gas ($O_2$/(Ar+$O_2$)) of 2, 3 and 5% as well as by changing the substrate temperature of $300^{\circ}C$ or $500^{\circ}C$. The influence of substrate pre-annealing and pre-cleaning on the quality of ITO film were examined, in which the substrate temperature was $500^{\circ}C$ and oxygen partial pressure was 3%. The characteristics of films were examined by the 4-point probe, Hall effect measurement system, SEM, AFM, Spectrophotometer, and X-ray diffraction. The optimum ITO films have been obtained when the substrate temperature is $500^{\circ}C$ and oxygen partial pressure is 3%. At optimum condition, the film showed transmittance of 81%, sheet resistivity of $226\Omegatextrm{cm}^2$, resistivity($\rho$) of $5.4\times10^{-3}\Omega$cm, carrier concentration of $1.0\times10^{19}cm^{-3}$, and carrier mobility of $150textrm{cm}^2$Vsec. From XRD spectrum, c(222) plane was dominant in the case of substrate temperature at $300^{\circ}C$, without regarding to oxygen partial pressure. However, in the case of substrate temperature at $500^{\circ}C$, c(400) plane was grown together with c(222) plane, only for oxygen partial pressure of 2 and 3%. In both case of chemical and ultrasonic cleaning without pre-annealing the substrate, it showed much almost same sheet resistivity, resistivity($\rho$), transmittance, carrier concentration, and carrier mobility. In case of $500^{\circ}C$/60min pre-annealing before ITO film deposited, both transimittance and carrier mobility are better than no pre-annealing, because pre-annealing is supposed to remove alkari ions diffusion from substrate. ITO film deposited on the Corning 0080 sybstrate showed a little bit better sheet resistivity, resistivity($\rho$), transimittance, carrier concentration than the film deposited on commercial glass. But no differences between Corning substrate and pre-annealed commercial glass substrate are found.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.3
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• pp.253-260
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• 2024

In this study, ITO thin films were fabricated on a glass substrate at different thicknesses without introducing oxygen using RF sputtering system. The structural, electrical, and optical properties were evaluated at various thicknesses ranging from 50 to 300 mm. As the thickness of deposited ITO thin film become thicker from 50 to 100 mm, carrier concentration, mobility, and band gap energy also increased while the resistivity and transmittance decreased in the visible light region. When the film thickness increased from 100 to 300 mm, the carrier concentration, mobility, and band gap energy decreased while the resistivity and transmittance increased. The optimum electrical properties were obtained for the ITO film 100 nm. After optimizing the thickness, the ITO thin films were post-annealed at different temperatures ranging from 100 to 300℃. As the annealing temperature increased, the ITO crystal phase became clearer and the grain size also increased. In particular, the ITO thin film annealed at 300℃ indicated high carrier concentration (4.32 × 10²¹ cm^-3), mobility (9.01 cm²/V·s) and low resistivity (6.22 × 10^-4 Ω·cm). This means that the optimal post-annealing temperature is 300℃ and this ITO thin film is suitable for use in solar cells and display application.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1203-1205
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• 2007

Confinement of charge carrier and exciton is the essential factor for enhancing the efficiency and stability of the electrophosphorescent devices. The interplay between the properties of emitters and other adjacent layers are studied based on the physical interpretation with difference of energy level, charge carrier mobility, and corresponding charge-trapping behavior.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.899-902
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• 1999

본 논문에서는 다수 반송자에 의해 일어나는 산란현상을 고려한 반송자-반송자 산란(CCS) 이동도 모델을 구현하였다. 구현된 CCS 이동도 모델을 검증하기 위해 N/sup ＋/P 접합 다이오드에 대해 모의실험 한 후 MEDICI와 비교한 결과 장벽전위인 0.9〔V〕 미만과 이상에서 각각 2%와 6% 정도의 상대오차를 보였다. BJT의 콜렉터에 30〔V〕를 인가한 후 베이스 전압을 0.8〔V〕까지 증가시켜 모의실험 한 결과 베이스 전압베이스 전류 및 베이스 전압-컬렉터 전류 특성은 각각 4.41%, 6.10%의 최대 상대오차를 보였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.