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Pentacene-based Thin Film Transistors with Improved Mobility Characteristics using Hybrid Gate Insulator

  • Park, Chang-Bum (Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul Natinal University) ;
  • Jung, Keum-Dong (Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul Natinal University) ;
  • Jin, Sung-Hun (Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul Natinal University) ;
  • Park, Byung-Gook (Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul Natinal University) ;
  • Lee, Jong-Duk (Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul Natinal University)
  • Published : 2005.06.24
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Abstract

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

Keywords

References

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