• Journal of IKEEE
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• v.13 no.4
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• pp.9-14
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• 2009

This paper describes measurement of an on-ship power supply noise in mixed-signal integrated circuits. To measure the on-chip power supply noise, we can check the effects of analog circuits and compensate it. This circuit consists of two independent measurement channels, each consisting of a sample and hold circuit and a frequency to digital converter which has a buffer and voltage controlled oscillator(VCO). The time-based voltage information and frequency-based power spectrum density(PSD) can be achieved by a simple analog to digital conversion scheme. The buffer works like a unit-gain buffer with a wide bandwidth and VCO has a high gain to improve resolution. This circuit was fabricated in a 0.18um CMOS technology and has 2.06mV/count. The noise measurement circuit consumes 15mW and occupies $0.768mm^2$.

• Korean Chemical Engineering Research
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• v.47 no.2
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• pp.141-149
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• 2009

The Cu thin film material and process, which have been already used for metallization of CMOS(Complementary Metal Oxide Semiconductor), has been highlighted as the Cu metallization is introduced to the metallization process for giga - level memory devices. The recent progresses in the development of key elements in electrochemical processes like surface pretreatment or electrolyte composition are summarized in the paper, because the semiconductor metallization by electrochemical processes such as electrodeposition and electroless deposition controls the thickness of Cu film in a few nm scales. The technologies in electrodeposition and electroless deposition are described in the viewpoint of process compatibility between copper electrodeposition and damascene process, because a Cu metal line is fabricated from the Cu thin film. Silver metallization, which may be expected to be the next generation metallization material due to its lowest resistivity, is also introduced with its electrochemical fabrication methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.32-38
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• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.57-63
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• 2016

This paper describes implementation of the RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4g SUN sensor node transceiver modules. Design of the each module like VCO, prescaler, 1/N divider, ${\Delta}-{\Sigma}$ modulator, and common circuits of the PLL has been optimized to obtain high speed and low noise performance. Especially, the VCO has been designed with NP core structure and 13 steps cap-bank to get high speed, low noise, and wide band tuning range. The output frequencies of the implemented synthesizer is 1483MHz~2017MHz, the phase noise of the synthesizer is -98.63dBc/Hz at 100KHz offset and -122.05dBc/Hz at 1MHz offset.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.