• Title/Summary/Keyword: CMOS optical receiver

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6.25-Gb/s Optical Receiver Using A CMOS-Compatible Si Avalanche Photodetector

  • Kang, Hyo-Soon;Lee, Myung-Jae;Choi, Woo-Young
    • Journal of the Optical Society of Korea
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    • v.12 no.4
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    • pp.217-220
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    • 2008
  • An optical receiver using a CMOS-compatible avalanche photodetector (CMOS-APD) is demonstrated. The CMOS-APD is fabricated with $0.18{\mu}m$ standard CMOS technology and the optical receiver is implemented by using the CMOS-APD and a transimpedance amplifier on a board. The optical receiver can detect 6.25-Gb/s data with the help of the series inductive peaking effect.

A Power-adjustable Fully-integrated CMOS Optical Receiver for Multi-rate Applications

  • Park, Kangyeob;Yoon, Eun-Jung;Oh, Won-Seok
    • Journal of the Optical Society of Korea
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    • v.20 no.5
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    • pp.623-627
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    • 2016
  • A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10−9 bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

A 150-Mb/s CMOS Monolithic Optical Receiver for Plastic Optical Fiber Link

  • Park, Kang-Yeob;Oh, Won-Seok;Ham, Kyung-Sun;Choi, Woo-Young
    • Journal of the Optical Society of Korea
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    • v.16 no.1
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    • pp.1-5
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    • 2012
  • This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-${\mu}m$ by 200-${\mu}m$ optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-$mm^2$ area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only $120{\mu}W$ in the sleep mode.

Design of CMOS Optical Link Receiver for FTTH (FTTH용 CMOS Optical Link Receiver의 설계)

  • Kim Kyu-Chull
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.1
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    • pp.47-52
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    • 2004
  • This paper presents a CMOS optical receiver design featuring wide input dynamic range and low bit error rate suitable for FTTH application. We achieved 60dB input dynamic range for up to 100Mbps by controlling the PMOS feedback resistance of transimpedance preamplifier according to its output signal level. Auto-bias circuit is designed in current mirror configuration to minimize duty error. Circuit simulation has been performed using 2-poly, 3-metal, 0.6um CMOS process parameters. The designed receiver consumes less than 130mW at 100Mbps with 5V power supply.

Design of 250-Mbps 10-Channel CMOS Optical Receiver Away for Parallel Optical Interconnection (병렬 광 신호 전송을 위한 250-Mbps 10-채널 CMOS 광 수신기 어레이의 설계)

  • Kim, Gwang-O;Choe, Jeong-Yeol;No, Seong-Won;Im, Jin-Eop;Choe, Jung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.37 no.6
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    • pp.25-34
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    • 2000
  • This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

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A Burst-mode Optical Receiver for 1.25Gbps PON (1.25Gbps PON용 버스트 모드 광 수신기)

  • Ki, Hyeon-Cheol
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.5
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    • pp.49-54
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    • 2013
  • We designed a burst mode optical receiver for 1.25Gbps PON(Passive Optical Network), fabricated it using $0.8{\mu}m$ BiCMOS foundry. We minimized the loss of the data in the front of the burst by reducing AGC(Automatic Gain Control) signal generation time using an exponential amplifier. We confirmed that AGC of the burst mode optical receiver functioned well and showed good performance in measurement. However, although the eye of the eye pattern was opened the jitter characteristic was deteriorated due to the heavy waveform distortion.

Improved 20Mb/s CMOS Optical Receiver for Digital Audio Interfaces (디지털 오디오 인터페이스용 개선된 20Mb/s CMOS 광수신기)

  • Yoo, Jae-Tack;Kim, Gil-Su
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.3 s.357
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    • pp.6-11
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    • 2007
  • This paper proposes CMOS optical receivers to reduce effective area and pulse width distortion (PWD) in high definition digital audio interfaces. To mitigate effective area and PWD, proposed receivers include a frans-impedance amplifier (TIA) with dual output and a level shifter with threshold convergence, respectively. Proposed circuits are fabricated using $0.25{\mu}m$ CMOS process and measured result demonstrated the effective area of $270\times120{\mu}m^2$ and PWD of ${\pm}3%$ for the receiver with a dual output TIA, and the effective area of $410\times140{\mu}m^2$ and PWD of ${\pm}2%$ for the receiver with a threshold convergence level shifter.

A $120-dB{\Omega}$ 8-Gb/s CMOS Optical Receiver Using Analog Adaptive Equalizer (아날로그 어댑티브 이퀄라이저를 이용한 $120-dB{\Omega}$ 8-Gb/s CMOS 광 수신기)

  • Lee, Dong-Myung;Choi, Boo-Young;Han, Jung-Won;Han, Gun-Hee;Park, Sung-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.119-124
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    • 2008
  • Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

  • Jung, Hyun-Yong;Youn, Jin-Sung;Choi, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.443-450
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    • 2014
  • This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

Design of a 1-Gb/s CMOS Optical Receiver for POF Applications (1-Gb/s CMOS POF 응용 광수신기 설계)

  • Lee, Jun-hyup;Lee, Soo-young;Jang, Kyu-bok;Yu, Chong-gun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.241-244
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    • 2012
  • In this paper, three types of optical receivers are designed using a $0.35-{\mu}m$ standard CMOS technology for plastic optical fiber (POF) applications. Basic common-source transimpedance amplifier (CS-TIA), common-gate TIA (CG-TIA), and regulated-cascode TIA (RGC-TIA) are optimally designed, and their transimpedance gain (TZ gain), 3-dB bandwidth, and noise characteristics are compared and analyzed. As a result of simulations, the RGC-TIA indicates better TZ gain and 3-dB bandwidth than other topologies, and CS-TIA has the best noise performance. Each optical receiver occupies area of $0.35mm^2$.

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