Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of 250-Mbps 10-Channel CMOS Optical Receiver Away for Parallel Optical Interconnection

병렬 광 신호 전송을 위한 250-Mbps 10-채널 CMOS 광 수신기 어레이의 설계

  • Kim, Gwang-O (Dept.of Electronics Electric Engineering, University of Seoul) ;
  • Choe, Jeong-Yeol (Dept.of Electronics Electric Engineering, University of Seoul) ;
  • No, Seong-Won (Dept.of Electronics Electric Engineering, University of Seoul) ;
  • Im, Jin-Eop (Dept.of Electronics Electric Engineering, University of Seoul) ;
  • Choe, Jung-Ho (Dept.of Electronics Electric Engineering, University of Seoul)
  • 김광오 (서울 시립대학교 전자전기공학부) ;
  • 최정열 (서울 시립대학교 전자전기공학부) ;
  • 노성원 (서울 시립대학교 전자전기공학부) ;
  • 임진업 (서울 시립대학교 전자전기공학부) ;
  • 최중호 (서울 시립대학교 전자전기공학부)
  • Published : 2000.11.01
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Abstract

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

본 논문에서 범용의 CMOS 트랜지스터 공정을 사용하여 250-Mbps 10-채널 CMOS 광 수신기 어레이칩을 설계하였다. 이러한 광 수신기 어레이는 병렬 광 신호 전송 시스템의 성능을 결정하는 가장 중요한 블록이며 이를 CMOS 트랜지스터로 설계함으로써 낮은 단가의 시스템의 구현을 가능하게 하였다. 각 데이터 채널은 집적화 된 광 검출 소자 및 여러 단의 증폭기로 구성된 아날로그 프런트-엔드, D-FF (D-flip flop)과 칩 외부 구동기로 구성된 디지털 블록으로 구성되어 있다. 전체 칩은 광 수신기 어레이와 데이터의 동기식 복원을 위해 PLL (Phase-Lock Loop) 회로로 구성 되어있다. 설계한 광 수신기 어레이 칩은 0.65-㎛ 2-poly, 2-metal CMOS 공정을 사용하여 제작하였으며, 각 채널은 ±2.5V의 전원 전압에 대하여 330㎽의 소비 전력을 보였다.

Keywords

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