Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A $120-dB{\Omega}$ 8-Gb/s CMOS Optical Receiver Using Analog Adaptive Equalizer

아날로그 어댑티브 이퀄라이저를 이용한 $120-dB{\Omega}$ 8-Gb/s CMOS 광 수신기

  • Lee, Dong-Myung (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Choi, Boo-Young (Department of Information Electronics Eng., Ewha Womans University) ;
  • Han, Jung-Won (Department of Information Electronics Eng., Ewha Womans University) ;
  • Han, Gun-Hee (Department of Electrical and Electronic Eng., Yonsei University) ;
  • Park, Sung-Min (Department of Information Electronics Eng., Ewha Womans University)
  • 이동명 (연세대학교 전기전자공학과) ;
  • 최부영 (이화여자대학교 전자공학과) ;
  • 한정원 (이화여자대학교 전자공학과) ;
  • 한건희 (연세대학교 전기전자공학과) ;
  • 박성민 (이화여자대학교 전자공학과)
  • Published : 2008.06.25
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Abstract

Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

트랜스임피던스 증폭기는 전체 광 수신기의 성능을 결정하는 가장 핵심적인 블록으로써 높은 트랜스임피던스 이득과 기가 비트급의 넓은 대역폭을 요구한다. 본 논문에서는 아날로그 어댑티브 이퀄라이저를 이용하여 트랜스임피던스 증폭기의 대역폭을 보상하고, 리미팅 증폭기를 이용하여 전체 트랜스임피던스 이득을 증가 시키는 단일 칩 광 수신기의 아날로그 회로를 제안한다. $0.13{\mu}m$ CMOS 공정을 이용하여 설계한 광 수신기는 포스트 레이아웃 시뮬레이션 결과, $120dB{\Omgea}$의 트랜스임피던스 이득과 5.88GHz의 대역폭을 갖는다. 수동 인덕터 소자를 사용하는 대신 네거티브 임피던스 컨버터 회로를 적용함으로써 $0.088mm^2$의 매우 작은 칩 사이즈를 갖는다.

Keywords

References

  1. S. Radovanovic, A. Annema, and B. Nauta, "A 3-Gb/s Optical Detector in Standard CMOS for 850-nm Optical Communication," IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1706-1717, Aug. 2005 https://doi.org/10.1109/JSSC.2005.852030
  2. W. Chen and D. Lin, "A 90-dB$\Omega$ 10-Gb/s Optical Receiver Analog Front-End in a 0.18-$\mu$m CMOS Technology, " IEEE Trans. on VLSI Systems, vol. 15, no. 3, pp. 358-365, Mar. 2007 https://doi.org/10.1109/TVLSI.2007.893625
  3. C. Wu, C. Lee, W. Chen, and S. Liu, "CMOSWideband Amplifiers Using Multiple Inductive-Series Peaking Technique," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 548-552, Feb. 2005 https://doi.org/10.1109/JSSC.2004.840979
  4. B. Analui and A. Hajimiri, "Bandwidth Enhancement for Transimpedance Amplifiers," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1263-1270, Aug. 2004 https://doi.org/10.1109/JSSC.2004.831783
  5. W. Chen and R. Gan, "1.8V, Variable Gain Transimpedance Amplifiers with Constant Damping Factor for Burst-Mode Optical Receiver," IEEE RFIC Symposium, 2005
  6. C. Y. Wang, C. S. Wang, and C. K. Wang, "An 18-mW Two-Stage CMOS Transimpedance Amplifier for 10 Gb/s Optical Application," IEEE ASSCC, Jeju, Korea, 2007
  7. J. N. Babanezhad, "A 3.3-V analog adaptive line-equalizer for fast ethernet data connection," in Proc. IEEE CICC, May 1998, pp. 343-346
  8. G. P. Hartman, K. W. Martin, and A. Mclaren, "Continuous-time adaptive-analog coaxial cable equalizer in 0.5$\mu$m CMOS," in Proc. ISCAS, 1999, pp. 97-100
  9. S. Galal and B. Razavi, "10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-$\mu$m CMOS Technology," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2138-2146, 2003 https://doi.org/10.1109/JSSC.2003.818567
  10. E. Sacking and W. C. Fischer, "A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 Receiver," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1884-1888, Dec. 2000 https://doi.org/10.1109/4.890301
  11. K. Yoo, D. Lee, G. Han, S. Park, and S. W. Oh, "A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in0.18$\mu$m CMOS Using Negative Impedance Compensation," IEEE ISSCC, San Francisco, CA, USA, Feb. 2007, pp. 23-24
  12. W.-Z. Chen, Y.-L. Cheng, and D.-S. Lin, "A 1,8V, 10Gbps fully integrated CMOS optical receiver analog front end," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1388-1396, Jun. 2005 https://doi.org/10.1109/JSSC.2005.845970