• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.128-133
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• 2013

In this paper, octagonal inductors for RFIC designs was fabricated with 90nm CMOS Technology to compare its quality factor and the effective inductance as functions of radius and number of turn. The quality factor decreases as the inner radius and the number of metal turned increase. However, the effective inductance increases with the increasing the inner radius and the number of metal turned. Therefore, the inductor structure should be decided according to the relative importance of Q-factor and inductance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.42-48
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• 2016

In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1046-1055
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• 1994

In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.357-361
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• 2018

This paper presents an averaging current adjustment technique for reducing the pixel resistance variation in a bolometer-type uncooled infrared image sensor. Each unit pixel was composed of an active pixel, a reference pixel for the averaging current adjustment technique, and a calibration circuit. The reference pixel was integrated with a polysilicon resistor using a standard complementary metal-oxide-semiconductor (CMOS) process, and the active pixel was applied from outside of the chip. The averaging current adjustment technique was designed by using the reference pixel. The entire circuit was implemented on a chip that was composed of a reference pixel array for the averaging current adjustment technique, a calibration circuit, and readout circuits. The proposed reference pixel array for the averaging current adjustment technique, calibration circuit, and readout circuit were designed and fabricated by a $0.35-{\mu}m$ standard CMOS process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.198-206
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• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.249-256
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• 2009

As a wireless handset deals with multiple application standards concurrently, RF transmitters and power amplifiers are required to be more power efficient and reconfigurable. In this paper, we review the recent advances in the design of the power amplifiers and transmitters. Then, the systematic design approaches to improve the performance with the digital baseband signal processing are introduced for the next generation mobile handset.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.