• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.501-503
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• 2008

This paper presents the design of a 2.4 GHz low phase noise fully integrated LC Voltage-Controlled-Oscillator (VCO) in $0.18{\mu}m$ CMOS technology. The VCO is without any tail bias current sources for a low phase noise and, in which differential varactors are adopted for the symmetry of the circuit. At the same time, the use of differential varactors pairs reduces the tuning range, i.e., the frequency range versus VTUNE, so that the phase noise becomes lower. The simulation results show the achieved phase noise of -138.5 dBc/Hz at 3 MHz offset, while the VCO core draws 3.9mA of current from a 1.8V supply. The tuning range is from 2.28GHz to 2.55 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.650-656
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• 2016

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1117-1122
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• 2009

In this work, temperature sensor and control circuit for measuring temperature are proposed. The proposed circuit can be fabricated without additional CMOS fabrication process and the output of proposed circuit is digital value. The supply voltage is 5volts and the circuit is designed by using 0.5${\mu}m$ CMOS process. The circuit for measuring temperature consists of PWM control circuit, VCO, counter and register. consisted The frequency of PWM control circuit is 23kHz and the frequency of VCO is 416kHz, 1MHz and 2MHz, respectively. The circuit operation is analyzed by using SPICE.

• Journal of IKEEE
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• v.24 no.4
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• pp.975-981
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• 2020

A 10 GHz LC voltage-controlled oscillator (VCO), which controls an amplitude of output signal, is proposed to improve the phase noise. The proposed amplitude control circuit for the LC VCO consists of a peak detector, an amplifier, and a current source. The peak detector is performed detecting the lowest voltage of the output signal by using two diode-connected NMOSFET and a capacitor. The proposed 10 GHz LC VCO with an amplitude control circuit for output signal is designed using a 55 nm CMOS process with a supply voltage of 1.2 V. Its area is 0.0785 ㎟. The amplitude control circuit used in the proposed LC VCO reduces the amplitude variation 242 mV generated in the output signal of the conventional LC VCO to 47 mV. Furthermore, it improves the peak-to-peak time jitter from 8.71 ps to 931 fs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.79-86
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• 2004

This paper proposes a dual band Voltage Controlled Oscillator(VCO) with a standard 0.3${\mu}{\textrm}{m}$ CMOS process to generate 1.07GHz and 2.07GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) was capable of producing a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -102.55dBc/Hz and -95.88dBc/Hz at 2MHz offset from 1.07GHz and 2.07GHz, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.325-328
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• 2020

This paper demonstrated a voltage-controlled oscillator (VCO) using cost-effective (1-poly 6-metal) mixed signal standard CMOS process. To have the high-quality factor inductor in LC resonator with thin metal thickness, patterned-ground shields (PGS) was adopted under the spiral to effectively reduce the ac current of low resistive Si substrate. And, because of thin top-metal compared with that of RF option (2 ㎛), we make electrically connect between the top metal (M6) and the next metal (M5) by great number of via array along the metal traces. The circuit operated from 2.48 GHz to 2.62 GHz tuned by accumulation-mode varactor device. And the measured phase noise of LC VCO has -123.7 dBc/Hz at 1MHz offset at 2.62 GHz and the dc-power consumption shows 2.07 mW with 1.8V supply voltage, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.207-212
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• 2013

A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.509-510
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• 2008

본 논문은 $0.18{\mu}m$ CMOS 공정을 사용하여 2.5Gb/s CMOS CDR을 설계하였다. CML type의 논리게이트를 이용하여 보다 높은 주파수의 대역의 데이터를 복원하기 위한 위상비교기(PD)와 PD의 up과 down신호를 지연없이 루프필터(LF)에 공급하기 위한 전하점프(CP) 그리고 외부 스위치를 통해 VCO이득을 조절할 수 있는 링 타입의 VCO로 구성되었다. 또한 VCO의 부담을 줄이기 위하여 half-rate 클럭 테크닉을 사용하였다. Cadence tool을 사용하여 모의실험 및 layout을 하였다. VCO이득은 100MHz/V이고, 클릭 jitter는 rising일 때 27ps, falling일 때 32ps로 우수한 결과를 얻을 수 있었다. 테스트칩 제작은 매그나침 $0.18{\um}$ CMOS 공정을 이용하였다. 칩 사이즈는 PAD를 포함하여 $850um{\times}750um$이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.