• ETRI Journal
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• v.30 no.4
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• pp.516-525
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• 2008

This paper proposes a compact, energy-efficient, and smart gas sensor platform technology for ubiquitous sensor network (USN) applications. The compact design of the platform is realized by employing silicon-on-insulator (SOI) technology. The sensing element is fully integrated with SOI CMOS circuits for signal processing and communication. Also, the micro-hotplate operates at high temperatures with extremely low power consumption, which is important for USN applications. ZnO nanowires are synthesized onto the micro-hotplate by a simple hydrothermal process and are patterned by a lift-off to form the gas sensor. The sensor was operated at $200^{\circ}C$ and showed a good response to 100 ppb $NO_2$ gas.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.341-342
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• 2007

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.93-98
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• 2004

A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$. It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K${\times}$32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.

• Journal of Sensor Science and Technology
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• v.24 no.6
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• Journal of Sensor Science and Technology
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• v.22 no.4
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• pp.256-261
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• 2013

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Journal of IKEEE
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• v.23 no.2
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• pp.722-726
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• 2019

In this paper, we propose a low drop-out (LDO) regulator with improved power-supply rejection (PSR) characteristics in the high frequency region. In particular, an NMOS transistor with a high output resistance is added as a compensation circuit to offset the high frequency noise passing through the finite output resistance of the PMOS power switch. The elimination of power supply noise by the compensating transistor was explained analytically and presented as the direction for further improvement. The circuit was fabricated in a $0.35-{\mu}m$ standard CMOS process and Specter simulations were carried out to confirm the PSR improvement of 26 dB compared to the conventional LDO regulator at 10 MHz.

• ETRI Journal
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• v.40 no.6
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• pp.693-698
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• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.