• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Journal of Information Display
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• v.8 no.1
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• pp.1-5
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• 2007

We have developed a CMOS LTPS process which requires only five photolithographic masks and only one ion doping step. Drain/Source areas of NMOS TFTs were formed by PECVD deposition of a highly doped precursor layer while PMOS contact areas were defined by ion implantation. Single TFTs, inverters, ring oscillators and shift registers were fabricated. N and p-channel devices reached field effect mobilities of $173cm^2$/Vs and $47cm^2$/Vs, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.10
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• pp.1888-1892
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• 2008

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.399-401
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• 2008

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.458-465
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• 2004

To reaffirm the use of a mainstream CMOS process for designing passive-like attenuator structures, a linearly controlled variable attenuator is realized with 0.35${\mu}{\textrm}{m}$ 2-poly 4-metal CMOS process. It uses the П configuration for large attenuation range and suitable matching property. Compared to conventional passive-like CMOS attenuators, it is demonstrated that this work advances the frequency band from MHz to ㎓ (DC- l㎓), and reduces the size to 700${\mu}{\textrm}{m}$${\times}$300${\mu}{\textrm}{m}$.. Both simulation results and test results are provided. They show the improved linear relation between attenuation and control voltage. It is very useful in CDMA or GSM band, which uses under 1㎓ frequency band. An alternative topology, Bridged-T configuration, is proposed to get over the limit of applications by elevating operation bandwidth. The proposed topology covers over DC-2㎓ frequency band, which means that the proposed architecture can cover the tripleband (800MHz CDMA/GSM, 1.5㎓ GPS, 1.9㎓z PCS system) in applications as well. The simulation results are provided.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.5
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.