• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.89-93
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• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.393-396
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• 2018

Herein, a 94-GHz low-noise amplifier (LNA) using the 65-nm CMOS process is presented. The LNA is composed of a four-stage differential common-source amplifier and impedance matching is accomplished with transformers. The fabricated LNA chip shows a peak gain of 25 dB at 94 GHz and has a 3-dB bandwidth at 5.5 GHz. The chip consumes 46 mW of DC power from a 1.2-V supply, and the total chip area, including the pads, is $0.3mm^2$.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.41-52
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• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.21-27
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• 2015

An improved method based on direct extraction and simultaneous optimization is developed to determine model parameters of symmetric inductors fabricated by the high resistivity(HR) silicon-on-insulator(SOI) RF CMOS process. In order to improve modeling accuracy, several model parameters are directly extracted by Y and Z-parameter equations derived from two equivalent circuits of symmetric inductor and grounded center-tap one, and the number of unknown parameters is reduced using parallel resistance and total inductance equations. In order to improve optimization accuracy, two sets of measured S-parameters are simultaneously optimized while same model parameters in two equivalent circuits are set to common variables.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.168-172
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• 2003

This paper analyzes the output noise and the noise figure of common source MOSFET pair each input of which is separately driven in the different frequencies. This analysis is performed for concurrent dual band cascode CMOS LNA with double inputs and single output fabricated in $0.18{\mu}m$ CMOS process. Since both inputs and output are matched to near $50{\Omega}$ using on-chip inductors, the measured noise figures are much higher than those of usual CMOS LNA. But, the main concern of this paper is focused on the added noise features due to the other channel common source stage. The dual-band LNA results in noise figure of 4.54dB at 2.14GHz and 6.03dB at 5.25GHz for selectable operation and 7.44dB and 6.58dB for concurrent operation. The noise analysis explains why the added noise at each band shows so large difference.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.8
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• pp.784-789
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• 2011

In this paper, a tunable integrated transmitter leakage canceller based on an autotransformer for ultra-high-frequency (UHF) RFID readers is presented. The proposed TX leakage canceller consists of an autotransformer, a digital tuning capacitor, a voltage controlled tuning resistor, and a compensating amplifier, and it is designed using 0.13 ${\mu}m$ 1-poly 6-metal RF CMOS process. The simulation results show that the proposed structure has over 55 dB rejection characteristic between a transmitter and a receiver and a 2.5 dB of the RX insertion loss. The TX leakage canceller can be digitally tuned from 825 MHz to 985 MHz with the tuning capacitor and it can be fully integrated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.565-570
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• 2012

This paper has proposed a multi-channel low pass filter (LPF) for LTE-Advanced systems. The proposed LPF is an active-RC 5th chebyshev topology with three cut-off frequencies of 5 MHz, 10 MHz, and 40 MHz. A 3-bit tuning circuit has been adopted to prevent variations of each cut-off frequency from process, voltage, and temperature (PVT). To achieve a high cut-off frequency of 40 MHz, an operational amplifier used in the proposed filter has employed a PMOS cross-connection load with a negative impedance. A proposed filter has been implemented in a 0.13-${\mu}m$ CMOS technology and consumes 20.2 mW with a 1.2 V supply voltage.

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.326-332
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• 2016

A novel CMOS temperature sensor with binary output is implemented by using fully differential switched-capacitor circuits for resistorless implementation of the temperature sensor core. Temperature sensing is based on the temperature characteristics of the pn diodes implemented by substrate pnp transistors fabricated using standard CMOS processes. The binary outputs are generated by using the charge-balance principle that eliminates the division operation of the PTAT voltage by the bandgap reference voltage. The chip was designed in a MagnaChip $0.35-{\mu}m$ CMOS process, and the designed circuit was verified using Spectre circuit simulations. The verified circuit was laid out in an area of $950{\mu}m{\times}557 {\mu}m$ and is currently under fabrication.