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http://dx.doi.org/10.5515/KJKIEES.2018.29.5.393

Design of 94-GHz High-Gain Differential Low-Noise Amplifier Using 65-nm CMOS  

Seo, Hyun-woo (College of Information & Communication Engineering, Sungkyunkwan University)
Park, Jae-hyun (College of Information & Communication Engineering, Sungkyunkwan University)
Kim, Jun-seong (College of Information & Communication Engineering, Sungkyunkwan University)
Kim, Byung-sung (College of Information & Communication Engineering, Sungkyunkwan University)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.29, no.5, 2018 , pp. 393-396 More about this Journal
Abstract
Herein, a 94-GHz low-noise amplifier (LNA) using the 65-nm CMOS process is presented. The LNA is composed of a four-stage differential common-source amplifier and impedance matching is accomplished with transformers. The fabricated LNA chip shows a peak gain of 25 dB at 94 GHz and has a 3-dB bandwidth at 5.5 GHz. The chip consumes 46 mW of DC power from a 1.2-V supply, and the total chip area, including the pads, is $0.3mm^2$.
Keywords
Low Noise Amplifier; CMOS; W-Band;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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