• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.477-480
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• 2015

In this paper a low-voltage vibration energy harvesting circuit with MPPT(Maximum Power Point Tracking) control is proposed. By employing bulk-driven technique, the minimum operating voltage of the proposed circuit is as low as 0.8V. The designed MPPT control circuit traces the maximum power point by periodically sampling the open circuit voltage of a full-wave rectifier circuit connected to the piezoelectric device output and delivers the maximum available power to load. The proposed circuit is designed using a $0.35{\mu}m\;CMOS$ process, and the chip area including pads is $1.33mm{\times}1.31mm$. Simulation results show that the maximum power efficiency of the designed circuit is 85.49%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.361-364
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• 2013

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. A adaptive control method has been proposed to reduce these loses. In this method, however, occurrence of and overlapping time of two power transistors in CCM results in reduction of efficiency. In this paper, to overcome this problem a new adaptive control method in proposed, and a DC-DC boost converter with the proposed adaptive control and power switching has been designed in a 0.35um CMOS process. The designed converter outputs 3.3V from a input voltage of 2.5V. The switching frequency is 500kHz and the maximum power efficiency is 95.3% at a load current 150mA. The designed chip area is $1720um{\times}1280um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.484-487
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• 2015

This paper describes a dual-input battery charger with MPPT control using photovoltaic and piezoelectric energy. Each energy is harvested from photovoltaic cells and piezoelectric cells and is stored to each capacitor. The battery voltage is boosted by charger block and two energy sources are used as input to charge battery capacitor. A DC-DC boost converter is designed to boost the battery voltage, and inductor sharing technique is employed such that only one inductor is required. The time division ratio for piezoelectric cell and photovoltaic cell is set to 8:1. The proposed circuit is designed in a 0.35um CMOS process technology. The condition of battery capacitor is managed by battery management block and the battery voltage can be boosted up to 3V. The maximum efficiency of the designed entire system is 88.56%, and the chip area including pads is $1230um{\times}1330um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.397-400
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• 2015

In this paper a solar energy harvesting system with low-cost MPPT control for low duty-cycled sensor nodes is proposed. The targeted applications are environment, structure monitoring sensor nodes that are not required successively to operate, and MPPT(Maximum Power point Tracking) control using simple circuits is low-cost differently than existing MPPT control. The proposed MPPT control is implemented using linear relationship between the open-circuit voltage of a solar cell. The designed MPPT circuit traces the maximum power point by sampling periodically the open circuit voltage of the solar cell and delivers the maximum available power to the load. The proposed circuit is designed in 0.35um CMOS process. The designed chip area is $975um{\times}1025um$ including pads. Measured results show that the designed system can track the MPP voltage by sampling periodically the open circuit voltage of solar cell.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1068-1075
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• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.31-34
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• 2018

This paper presents a low-power buck-boost converter for multi-input energy harvesting systems. The designed circuit combines the energy harvested from three input channels in real time and stores it in a storage capacitor. The structure of the buck-boost converter is simplified by using one external inductor and applying time division technique using an arbiter. In addition, to improve the efficiency of the system, the controller circuits of the converter are designed so that current consumption is minimized. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. Simulation results show that the designed circuit consumes up to 490nA of current when all three input channels are active, and the maximum power efficiency is 92%. The chip area of the designed circuit is $1310{\mu}m{\times}1100{\mu}m$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.1
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• pp.82-89
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• 2014

Recently, inertial sensors are popularly used for the location and position recognition of small devices for M2M/IoT. In this paper, we designed low power, low noise, small sized 6-axis inertial sensor IC for mobile applications, which uses a 3-axis piezo-electric gyroscope sensor and a 3-axis piezo-resistive accelerometer sensor. Proposed IC is composed of 3-axis gyroscope readout circuit, two gyroscope sensor driving circuits, 3-axis accelerometer readout circuit, 16bit sigma-delta ADC, digital filter and control circuit and memory. TSMC $0.18{\mu}m$ mixed signal CMOS process was used. Proposed IC reduces 27% of the current consumption of LSM330.