• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1837-1844
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• 2009

In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Bulletin of the Korean Mathematical Society
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• v.53 no.4
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• pp.1071-1085
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• 2016

For $b{\in}L^1_{loc}({\mathbb{R}}^n)$, let ${\mathcal{I}}_{\alpha}$ be the bilinear fractional integral operator, and $[b,{\mathcal{I}}_{\alpha}]_i$ be the commutator of ${\mathcal{I}}_{\alpha}$ with pointwise multiplication b (i = 1, 2). This paper shows that if the commutator $[b,{\mathcal{I}}_{\alpha}]_i$ for i = 1 or 2 is bounded from the product Morrey spaces $L^{p_1,{\lambda}_1}({\mathbb{R}}^n){\times}L^{p_2,{\lambda}_2}({\mathbb{R}}^n)$ to the Morrey space $L^{q,{\lambda}}({\mathbb{R}}^n)$ for some suitable indexes ${\lambda}$, ${\lambda}_1$, ${\lambda}_2$ and $p_1$, $p_2$, q, then $b{\in}BMO({\mathbb{R}}^n)$, as well as that the compactness of $[b,{\mathcal{I}}_{\alpha}]_i$ for i = 1 or 2 from $L^{p_1,{\lambda}_1}({\mathbb{R}}^n){\times}L^{p_2,{\lambda}_2}({\mathbb{R}}^n)$ to $L^{q,{\lambda}}({\mathbb{R}}^n)$ implies that $b{\in}CMO({\mathbb{R}}^n)$ (the closure in $BMO({\mathbb{R}}^n)$of the space of $C^{\infty}({\mathbb{R}}^n)$ functions with compact support). These results together with some previous ones give a new characterization of $BMO({\mathbb{R}}^n)$ functions or $CMO({\mathbb{R}}^n)$ functions in essential ways.

• Clinical and Experimental Reproductive Medicine
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• v.15 no.2
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• pp.83-92
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• 1988

혈액에서 생물학적 활성을 나타내는 (bioavailable) steroid hormone은 주로 비결합형(free form)과 알부민 결합형(albumin-bound form)으로 구성된다. 특히 Testosterone (T)과 5 alpha-Dihydrotestosterone (DHT)의 활성적 분획이 전체의 T, DHT 양에 비해 생리적 현상과 보다 잘 일치하는 것으로 알려지고 있다. 본 연구는 섬광면역측정법(Luminescence immunoassay, LIA)으로 혈청내 활성적 T 및 DHT의 농도의 측정에 이용하고져 하였다. 항체는 T- 또는 DHT-3-CMO-BSA를 항원으로 토끼에 면역주사하여 얻었다. 추적자는 T-3-CMO, DHT-3-CMO에 aminobutylethylisoluminol(ABEI)를 부착시켜 사용하였다. 항체중 IgG분획을 Protein-A-Sepharose CL-4B로 분리한 후 Immunobead(Bio-Rad)에 부착시켜 Solid-phase LIA를 실시하였다. 본 연구에서 LIA는 정확도(accuracy), 정밀도(precision), 감도(sensitivity), 교차반응도(specificity)등을 조사하고, 기존의 방사면역측정법(RIA)과 비교하여 만족할만한 결과를 얻었다. 혈청내 T및 DHT의 활성적 분획의 농도를 측정한 결과는 다음과 같았다. T의 경우는 남성에서 T의 전체량의 33% 이상으로 $7.1{\pm}1.5nmol/l$, 여성에서는 26% 이상으로 $0.28{\pm}0.05nmol/l$이었다. DHT의 활성적 분획은 남성의 경우 $601.7{\pm}85.8pmol/l$, 여성의경우 $52.4{\pm}19.9\;pmol/l$이었다. 이상의 결과를 보아 본 연구에서 이용된 LIA는 혈청내 활성적 농도를 측정하기에 충분하다고 사료된다. 또한 이 방법을 이용하여 여성의 Androgenicity 및 남성 정소기능등의 제어방법에 응용될 수 있을 것으로 판단된다.

• Journal of Electrochemical Science and Technology
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• v.12 no.2
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• pp.246-256
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• 2021

Mo,Cu-doped CeO₂ (CMCuO) nanopowders were synthesized by the nitrate-fuel combustion method aiming to improve the electrical and electrochemical properties of its Mo-doped CeO₂ (CMO) parent by the addition of copper. An electrical conductivity of ca. 1.22·10^-2 S cm^-1 was measured in air at 800℃ for CMCuO, which is nearly 10 times higher than that reported for CMO. This increase was associated with the inclusion of copper into the crystal lattice of ceria and the presence of Cu and Cu₂O as secondary phases in the CMCuO structure, which also could explain the increase in the charge transfer activities of the CMCuO based anode for the hydrogen and carbon monoxide electro-oxidation processes compared to the CMO based anode. A maximum power density of ca. 120 mW cm^-2 was measured using a CMCuO based anode in a solid oxide fuel cell (SOFC) with YSZ electrolyte and LSM-YSZ cathode operating at 800℃ with humidified syngas as fuel, which is comparable to the power output reported for other SOFCs with anodes containing copper. An increase in the area specific resistance of the SOFC was observed after ca. 10 hours of operation under cycling open circuit voltage and polarization conditions, which was attributed to the anode delamination caused by the reduction of the Cu₂O secondary phase contained in its microstructure. Therefore, the addition of a more electroactive phase for hydrogen oxidation is suggested to confer long-term stability to the CMCuO based anode.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• IT SoC Magazine
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• s.1
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• pp.37-41
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• 2004

전력이라는 장벽 때문에 공정 스케일링은 점점 어려워지고 있다. 반면, 미래의 컴퓨터와 통신은 더더욱 낮은 전력 소모를 필요로 한다. 아직은 에너지 효율적인 공정이 널리 보급되고 있지 않으므로, 저전력 CMOS SoC 설계는 여전히 큰 어려움이 있다. 본문에서는 CMOS의 전력 감소를 위해 무엇을 어떻게 해야 하는지 알아보도록 한다.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.1-8
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• 1998

In this paper, we designed a low power 8bit ELM adder with static CMOS and hybrid logic styles on a chip. The designed 8bit ELM adder with both logic styles was fabricated in a 0.8$\mu\textrm{m}$ single-poly double-metal, LG CMOS process and tested. Hybrid logic style consists of CCPL(Combinative Complementary Pass-transistor Logic), Wang's XOR gate and static CMOS for critical path which determines the speed of ELM adder. As a result of chip test, the ELM adder with hybrid logic style is superior to the one with static CMOS by 9.29% in power consumption, 14.9% in delay time and 22.8% in PDP(Power Delay Product) at 5.0V supply voltage, respectively.

• Journal of IKEEE
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• v.26 no.1
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• pp.111-118
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• 2022

In this paper, we studied 4H-SiC CMOS that can be integrated with high-voltage SiC power devices. After designing the CMOS on a 4H-SiC substrate, we compared the electrical characteristics with the reliability of high temperature operation by TCAD simulation. In particular, it was confirmed that changing HfO₂ as the gate dielectric for reliable operation at high temperatures improves the thermal properties compared to SiO₂. By researching SiC CMOS devices, we can integrate high-power SiC power devices with SiC CMOS for excellent performance in terms of efficiency and cost of high-power systems.