• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.11
• /
• pp.2643-2648
• /
• 2015

This paper analyzes the phenomenon of drain induced barrier lowering(DIBL) for doping profiles in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to the change of doping profile to influence on potential distribution. As a results, the DIBL is significantly influenced by projected range and standard projected deviation, the variables of channel doping profiles. The change of DIBL shows greatly in the range of high doping concentration such as $10^{18}/cm^3$. The DIBL increases with decrease of channel length and increase of channel thickness, and with increase of bottom gate voltage and top/bottom gate oxide film thickness.

• Journal of the Korean Vacuum Society
• /
• v.8 no.4A
• /
• pp.490-495
• /
• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• Journal of Korea Water Resources Association
• /
• v.33 no.2
• /
• pp.237-245
• /
• 2000

Sihwa seadike is originally designed to control the water level In lake Sihwa. However the sluice gate is being operated everyday to preserve the water quality of lake. Due to the frequent operation of gates the bottom of drainage canal which is composed of weathered rock and soft rock is being scoured. Recently the bottom in the front area of apron was protected by putting underwater concrete. This study is carried out to understand the hydraulic situation for protection, and to estimate the trend of scouring by comparing between energy dissipation and registance of bottom rock. Annandale(1995) introduced the erodibility index theory, and suggested a criteria to judge the erodibility of rock through the relation between the erodibility index and energy dissipation. Determenation of erodibility index of rock is based on the results of sample core analysis, and the energy dissipation of flow is calculated from the estimation of total head on the scale model. These two values are plotted on the criteria, and the erodibility of rock is determined.

• Electrical & Electronic Materials
• /
• v.9 no.3
• /
• pp.277-283
• /
• 1996

The temperature dependent characteristics of hydrogenerated amorphous silcon thin film transistor (a-Si:H TFT) with a bottom gate of N-Type <100> Si wafer were investigated. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the gate voltage increased and decreased with the small gate voltage. According to the variation of gate voltages, drain current of TFT increased by temperature increase, and hysteresis characteristics mainly depended on the temperature increase. The hysteresis current showed negative characteristics curve over 383K. The hysteresis occurance area and the differences of forward and reverse sweep were increased at the higher temperature. Hysteresis current of I$_{d}$(on/off) ratio decreased at the lower temperature and increased at the higher temperature.e.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.101-104
• /
• 2008

Too high stress of the bottom Mo layer of the gate line is thought to be the main reason for H-line mura. H-Line mura is eliminated effectively by changing the gate line metal structure from Mo/AlNd/Mo to AlNd/Mo. The new structure does not influence the panel's electrical characteristics.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.1119-1122
• /
• 2005

A selective deposition of Co thin films for thin film transistor gate electrode has been carried out by the growth with combination of micro-contact printing and metal organic chemical vapor deposition (MOCVD). This results in the elimination of optical lithography process. MOCVD has been employed to selectively deposit Co films on preformed OTS gate pattern by using micro-contact printing (${\mu}CP$). A hydrogenated amorphous silicon TFT with a Co gate selectively formed on SAMs patterned structure exhibited a subthreshold slope of 0.88V/dec, and mobility of $0.35cm^2/V-s$, on/off current ratio of $10^6$, and a threshold voltage of 2.5V, and thus demonstrating the successful application of the novel bottom-up approach into the fabrication of a-Si:H TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1995.05a
• /
• pp.43-46
• /
• 1995

We fabricate a bottom gate a-Si:H TFT on N-Type <100> Si wafer. According to the variation of gate and drain voltage, the hysteresis characteristic curves were measured experimentally. Also, we showed that the model predict the hysteresis characteristic successfully. Drain current on the hysteresis characteristic currie showed an exponential variation. Hysteresis area of TFT increased with the drain voltage increase and decreases with the drain voltage decrease.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.108-110
• /
• 2018

This paper proposes shortcircuit fault protection method in a synchronous buck converter using the PCB pattern Rogowski coil. The PCB pattern Rogowski coils are embedded in the gate driver to measure the device currents of the top and bottom side. When shortcircuit occurs in the system, the gate signal is blocked by the proposed fault protection method using the device current. The simulation and experimental results show that the proposed fault protection method is verified in the shortcircuit system.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.43 no.7
• /
• pp.1135-1143
• /
• 1994

We fabricate a bottom gate a-Si:H TFT on N-Type <100> Si wafer. According to the Variation of gate and drain voltage, the hysteresis characteristic curves were measured experimentally. Also, we proposed model equation and showed that the model predict the hysteresis characteristic successfully. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the drain voltage increase and decreases with the drain voltage decrease.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.102-108
• /
• 2013

In manufacturing of solution-processed organic electronic devices, a spin coating method is frequently used, but which has a big problem. Solvent in a solution has a decisive effect such as physical and chemical damage for successive solution-based film deposition. Such a severe damage by solvent restricts for fabricating building blocks of multi-layered films from solutions. In this work, it will be shown that a proper combination of well-known solvents gives a chance to fabricate multi-layered film, also this new method was applied to make organic field effect transistor. Two types of bottom gate, bottom contact transistors were fabricated, one of which is fabricated by conventional single spin coating method, the other fabricated by double spin coating method. Compared with the electrical characteristics in a single spin coated transistor, the leakage current between source and gate electrode was decreased, ON state current was increased, and the extracted saturation mobility was multiplied more than 2.7 time for double spin coated transistors. It is suggested that the multiple coated gate dielectric structure is more desirable for high performance organic ferroelectric field effect transistors.