Mathematical Modeling of Hysteresis Characteristics of a-Si:H TFT

비정질 실리코 박막 트랜지스터 히스테리시스 특성의 수학적인 모델

We fabricate a bottom gate a-Si:H TFT on N-Type <100> Si wafer. According to the Variation of gate and drain voltage, the hysteresis characteristic curves were measured experimentally. Also, we proposed model equation and showed that the model predict the hysteresis characteristic successfully. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the drain voltage increase and decreases with the drain voltage decrease.