• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.473-473
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• 2000

This paper presents the 2-bit parallel algorithmic ADC using current mode for parallel method algorithm. It is operated by parallel conversion, 2-bit at each moment, and increase bit numbers by serial connection. The circuit operates in current mode. The comparison ratio can be controlled while working under mode operation. The circuit design used 0.8 ${\mu}{\textrm}{m}$ CMOS technology which capable to convert 2-bit in 50 ns, power consumed 0.786 nW, with input current 0-50 mA from 3V single supply. From simulation testing, the conversion rate is much faster than other method.

• Journal of IKEEE
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• v.17 no.3
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• pp.260-266
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• 2013

The open bit line is vulnerable to noise compared to the folded bit line when read/write for the DRAM. According to the increasing DRAM densities, the core circuit operating conditions is exacerbated by the noise when it comes to the open bit line 6F2(F : Feature Size) structure. In this paper, the interference effects were analyzed by the data patterns between the bit line by experiments. It was beyond the scope of existing research. 68nm Tech. 1Gb DDR2, Advan Tester used in the experiments. The noise effects appears the degrade of internal operation margin of DRAM. This paper investigates sense amplifier power line splits by experiments. The noise can be improved by 0.2ns(1.3%)~1.9ns(12.7%), when the sense amplifier power lines split. It was simulated by 68nm Technology 1Gb DDR2 modeling.

• International Journal of Precision Engineering and Manufacturing
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• v.8 no.1
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• pp.21-26
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• 2007

In industry, multihead automatic combination weighers are used to provide accurate weights at high speed. To minimize giveaway, greater accuracy is desired, especially for valuable products. This paper describes a combination algorithm based on bit operation. The combination method is simple and saves time, since only the elements to be considered for combination are generated. The total number of combinations from which the desired output weight is chosen can be increased by extending the combination from memory hoppers to include some weighing hoppers. For an eight-channel weigher, three or four combination elements are best. In addition to targeting approximately equal amounts of products in each channel, this study investigated other schemes. Simulation results show that schemes targeting combination elements with an unequal distribution of the output weight are more accurate. The most accurate scheme involves supplying products to all memory and weighing hoppers before commencing the combination operation. However, this scheme takes more time.

• ETRI Journal
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• v.25 no.5
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• pp.315-320
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• 2003

Elliptic curve cryptography (ECC) offers the highest security per bit among the known public key cryptosystems. The operation of ECC is based on the arithmetic of the finite field. This paper presents the design of a 193-bit finite field multiplier and an inversion unit based on a normal basis representation in which the inversion and the square operation units are easy to implement. This scalable multiplier can be constructed in a variable structure depending on the performance area trade-off. We implement it using Verilog HDL and a 0.35 ${\mu}m$ CMOS cell library and verify the operation by simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.173-179
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• 2002

We propose a novel sensing circuit for 2T-2MTJ MRAM that can be used for high speed synchronous operation. Proposed bit-line sense amplifier detects small voltage difference in bit-lines and develops it into rail-to-rail swing while maintaining small voltage difference on TMR cells. It is small enough to fit into each column that the whole data array on selected word line are activated as in DRAMs for high-speed read-out by changing column addresses only. We designed a 256Kb read-only MRAM in a $0.35\mu\textrm{m}$ logic technology to verify the new sensing scheme. Simulation result shows a 25ns RAS access time and a cycle time shorter than 10 ns.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.309-322
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• 2021

In this study, an extension instruction set for high-speed operation of the ARIA block cipher algorithm on RISC-V processor is added to support high-speed cryptographic operation on low performance IoT devices. We propose the efficient ARIA cryptographic instruction set which runs on a conventional 32-bit processor. Compared to the existing software cryptographic operation, there is a significant performance improvement with proposed instruction set.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.567-572
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• 2019

In this paper, we propose an algorithm to perform convolution, pooling, and ReLU operations in CNN using binary image and binary kernel. It decomposes 256 gray-scale images into 8 bit planes and uses a binary kernel consisting of -1 and 1. The convolution operation of binary image and binary kernel is performed by addition and subtraction. Logically, it is a binary operation algorithm using the XNOR and comparator. ReLU and pooling operations are performed by using XNOR and OR logic operations, respectively. Through the experiments to verify the usefulness of the proposed algorithm, We confirm that the CNN operation can be performed by converting it to binary logic operation. It is an algorithm that can implement deep running even in a system with weak computing power. It can be applied to a variety of embedded systems such as smart phones, intelligent CCTV, IoT system, and autonomous car.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1419-1424
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• 2005

This paper suggests a new cipher mode of operation which can recover cryptographic synchronization. First, we study the typical cipher modes of operation, especially focused on cryptographic synchronization problems. Then, we suggest a statistical cipher-feedback mode of operation. We define the error sources mathmatically and simulate propagation errors caused by a bit insertion or bit deletion. In the simulation, we compare the effects of changing the synchronization pattern length and feedback key length. After that, we analyze the simulation results with the calculated propagation errors. finally. we evaluate the performance of the statistical cipher-feedback mode of operation and recommand the implementation considerations.