1 |
Bodhisattva Das, William C. Black, Jr., and Arthur V. Pohm, 'Universal HSPICE Macromodel for Giant Magnetoresistance Memory Bits' IEEE transactions on magnetics, Vol. 36, NO. 4, JULY 2000
DOI
ScienceOn
|
2 |
Tzu-Ning Fang and Jian-Gang Zhu, '2D Write Addressability of tunneling Junction MRAM elements,' IEEE transactions on magnetics, Vol. 37, NO. 4, JULY 2001
DOI
ScienceOn
|
3 |
Geral B. Granley, Allan T. Hurst, ' Projected Applications, Status and Plans For Honeywell. High Density, High Performance, Nonvolatile Memory (combined papers)' 1996 lnt'l Nonvolatile Memory Technology Conference
DOI
|
4 |
Peter K. Naji, Mark Durlam, Saied Tehrani, John Calder and Mark F. DeHerrera, 'A 256kb 3.0V ITIMTJ Nonvolatile Magnetoresistive RAM' ISSCC 2001
DOI
|
5 |
Kouichi Yamada, Naofumi Sakai, Yoshiyuki Ishizuka and Kazunobu Mameno, 'A Novel Sensing Scheme for a MRAM with a 5% MR Ratio' 2001 SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS
DOI
|
6 |
R. E. Scheuerlein, W. J. Gallagher, S. S. P. Parkin, C. A. Lee, S. T. Roy, R. Robertazzi, W. R. Reohr, 'A 10ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell', ISSCC Digest of technical papers, vol.43, pp.128-129, Feb., 2000
DOI
|
7 |
M. Durlam, P. Naji, M. DeHerrera, S. Tehrani, G. Kerszykowski and K. Kyler, 'Nonvolatile RAM based on Magnetic Tunnel Junction Elements' ISSCC 2000
DOI
|
8 |
Roy E. Scheuerlein, 'Magneto-Resistive IC Memory Limitations and Architecture Implications' 1998 Int'l Nonvolatile Memory Technology Conference
DOI
|