• 전기학회논문지
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• 제58권10호
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• 한국멀티미디어학회논문지
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• 제17권3호
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• 전기학회논문지
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• 제59권3호
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• 수산해양교육연구
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• 제23권2호
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• pp.162-181
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• 2011

The purpose of this study was to reveal controversial issues on Stages of Concern(SoC), which is one of the dimensions of Concerns Based Adoption Model(CBAM). To achieve the purpose, documental analysis was employed. The theoretical framework to analyze literature consisted of three categories including stages, measurements, and applications. Based on the framework, controversial issues on SoC were discussed regarding arguments of CBAM developers and critics. The researchers of this study suggested their own opinions on the issues after thorough examination of CBAM developer's arguments and oppositions against them. Finally, suggestions for further studies on issues of SoC and studies measuring SoC were made.

• 전기학회논문지
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• 제58권7호
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• pp.1418-1423
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• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• 전기학회논문지
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• 제60권1호
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• pp.156-160
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• 2011

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

• 한국멀티미디어학회논문지
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• 제18권2호
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• pp.244-252
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• 2015

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.

• 한국컴퓨터정보학회논문지
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• 제18권8호
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• pp.33-41
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• 2013

최근 지능형자동차 기술은 IT와 융합되어 새로운 첨단 영상미디어 응용기술로 발전하며, 오픈소스 기반의 안드로이드를 탑제한 스마트폰 응용기술과 지능형자동차 개발이라는 새로운 패러다임으로 많은 연구개발이 이루어지고 있다. 안드로이드 기반의 지능형자동차 응용 기술은 이동수단의 한계를 넘어 다양한 멀티미디어 중심의 집합기술로 진화하고 있으며, 이러한 분산 환경에서 개발되어 있는 각각의 멀티미디어 플랫폼서비스와 애플리케이션이 개발되고 있음에 따라 다양한 서비스 기술을 통한 휴대 단말장치기술이 절대적으로 요구되고 있다. 본 논문에서는 안드로이드 기반의 지능형 자동차 전용 미들웨어 설계를 통하여 단일형 시스템 스펙에 맞춰 SVC Codec과 실시간 동영상, 그래픽처리등 지능형자동차 미들웨어 SoC 설계를 통해 응용 연구를 실험 하였으며, 오픈플랫폼에서 제공되는 각종 단말서비스 기능들을 SoC 기반으로 새롭게 설계하고 표준화된 인터페이스 분석기법을 본 연구에서 실험을 통하여 입증하였다.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.86-94
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• 2007

네트워크-온-칩(NoC, network-on-chip) 기술은 SoC (system-on-a-chip) 설계에서 증가되는 온칩 통신의 복잡성을 해결하고 높은 확장성을 제공할 수 있는 기술이다. NoC를 이용한 설계는 많은 수의 IP들과 통신 네트워크들을 사용하기 때문에 동작이 복잡하고 설계 공간이 커서 많은 전력을 소모 한다. 그러나 기존의 분석적인 방법은 NoC응용의 큰 설계 공간 및 동작의 복잡성에 비해 상대적으로 간소화된 모델을 사용하여 현실적인 설계요소를 반영하지 못하거나 복잡한 시뮬레이션에 따른 많은 노력 및 시간 요구로 사용에 많은 제약이 있었다. 따라서 본 논문에서는 현실적이고 정확한 NoC의 전력 소모 분석을 위해 FPGA 프로토타입(prototype)을 개발하고 이에 대한 전력 소모를 분석을 할 수 있는 싸이클별 전력 소모 측정 기법 및 도구를 소개한다. 또한 사례 연구로서 NoC기술을 이용한 JPEG 압축기를 구현하고 이에 대한 전력 소모를 분석하여 그 효용성을 입증한다.

• 대한임베디드공학회논문지
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• 제2권1호
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• pp.24-30
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• 2007

According to development of wireless communication technologies, we need not only high data rate but low data rate system of low power consumption. This low data rate system is utilized in the field of home automation, health care, sensoring and monitoring, etc. IEEE 802.15.4 LR-WPAN system is the best choice for realizing ubiquitous networking system. In this paper SoC Architecture for IEEE 802.15.4 Low Rate WPAN is designed. IEEE 802.15.4 Low Rate WPAN system serves the functions and realization of home area network. We propose the SoC architecture for 868/915MHz frequency band of IEEE 802.15.4 Low Rate WPAN system. The key issue is to design SoC architecture which provides the function of Low Rate WPAN system to meet the requirement of IEEE 802.15.4 standards.