1 |
A. Pentland and T. Choudhury, "Face Recognition for Smart Environments," IEEE Computer, Vol. 33, No. 2, pp. 50-55, 2000.
|
2 |
J.M. Zurada, Introduction to Artificial Neural Systems, PWS Publishing Company, 1992. New Jersey.
|
3 |
T. Schoenauer, A. Jahnke, U. Roth, and H. Klar, "Digital Neurohardware: Principles and Perspectives," Neuronal Networks in Applications, pp. 101-106, Vol. 2, No. 20, 1998.
|
4 |
K. Mathia, J. Clark, B. Colbert, and R. Saeks, "Benchmarking and MIMD Neural Network Processor," WCNN'96, pp. 1203-1210, 1996.
|
5 |
M. Nahvi and A. Ivanov, "Indirect Test architecture for SoC Testing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 7, pp. 1128-1142, 2004.
DOI
ScienceOn
|
6 |
T. Theocharides, G. Link, N. Vijaykrishnan, M.J. Irwin, and W. Wolf, "Embedded Hardware Face Detection," Proc. the 17th International Conference on VLSI Design, pp. 569-572, 2004.
|
7 |
M. Brogatti, F. Lertora, B. Foret, and L. Cali, "A Reconfigurable System Featuring Dynamically Extensible Embedded Microprocessor, FPGA, and Customizable I/O", IEEE Journal of Solid-State Circuits, Vol. 38, Issue 3, pp. 521-529, 2003.
DOI
ScienceOn
|
8 |
T.H. Tsai, Y.C. Yang, and C.N. Liu, "A Hardware/Software Co-Design of MP3 Audio Decoder," The Journal of VLSI Signal Processing Systems for signal, Image and Video Technology, Vol. 41, Issue 1, pp. 111-127, 2005.
DOI
|
9 |
E.M. Oritigosa, A. Canas, E. Ros, P.M. Ortigosa, S. Mota, and J. Diaz, "Hardware Dscription of Multi-Layer Perceptrons with Different Abstraction Levels," Microprocessors and Microsystems, Vol. 30, Issue 7, pp. 435-444, 2006.
DOI
ScienceOn
|
10 |
S. Vitabile, V. Conti, F. Gennaro, and F. Sorbello, "Efficient MLP Digital Implementation on FPGA," Proc. the 8th Euromicro Conference on DSD, pp. 124-129, 2005.
|
11 |
A. Rosado-Munoz, E. Soria-Olivas, L. Gomez- Chova, and J.V. Frances, "An IP Core and GUI Implementing Multilayer Perceptron with a Fuzzy Activation Function on Configurable Logic Devices," Journal of Universal Computer Science, Vol. 14, No. 10, pp. 1678-1694, 2008.
|
12 |
M. Pormann, M. Franzmeier, H. Kalte, U. Witkowski, and U. Ruckert, "A Reconfigurable SOM Hardware Accelerator," Proc. the European Symposium on Artificial Neural Networks Bruges(Belgium), pp. 337-342, 2002.
|
13 |
LEON2 Processor User's Manual, http://www. gaisler.com, 2004
|
14 |
M.S. Islam, M.S. Beg, M.S. Bhuyan, and M. Othman, "Design and Implementation of Discrete Cosine Transform Chip for Digital Comsumer Products," IEEE Transaction on Consumer Electronics, Vol. 52, No. 3, pp. 998-1003, 2006.
DOI
ScienceOn
|
15 |
J.H. Lee and S.C. Kim, "Analysis of Verification Methodologies based on a SoC Platform Design," International Journal of Contents, Vol. 7, Issue 1, pp. 23-28, 2011.
DOI
ScienceOn
|
16 |
P.G.D. Valle, D. Atienza, G. Paci, and F. Poletti, "Application of FPGA Emulation to SoC Floorplan and Packaging Exploration," Proc. the XXI I Conference on Design of Circuits and Integrated System, pp. 236-240, 2007.
|
17 |
S.M. Shon, S.H. Yang, S.W. Kim, K.H. Baek, and W.H. Paik, "Soc Design of an Auto Focus Driving Image Signal Processor for Mobile Camera Applications," IEEE Transactions on Consumer Electronics, Vol. 52, Issue 1, pp. 10-16, 2006.
DOI
ScienceOn
|
18 |
H. Nakajima, Y. Matsuo, M. Nagata, and K. Saito, "Portable Translator Capable of Recognizing Characters on Signboard and Menu Captured by Built-In Camera," Proc. the ACL Interactive Poster and Demonstration Sessions, pp. 61-64, 2005.
|
19 |
B. Lee, Y. Cho, and S. Cho, "Translation, Scale and Rotation Invariant Pattern Recognition using PCA and Reduced Second Order Neural Network" Neural, Parallel & Scientific Computation, Vol. 3, Issue 3, pp. 417-429, 1995.
|
20 |
MT9V112 Manual, http://www.micron.com, 2005
|
21 |
M.Y. Na, H. J. Kim and T. Y. Kim, "An Illumination and background-Robust Hand Image Segmentation Method based on Dynamic Threshod Values," Journal of Korea Multimedia Society, Vol. 14, No. 5, pp. 607-613, 2011.
DOI
ScienceOn
|