• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.372-376
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• 2001

Due to several advantages of Pulse Width Modulation(PWM) Converter, such as unity power factor operation, elimination of low-order harmonics and regeneration of motor braking energy to source, the application range of PWM Converter has been rapidly extended in industrial application. Nowadays, vector control algorithm and space vector PWM(SVPWM) method are applied to improve the performances of PWM Converter, but vector control algorithm and SVPWM require to use Microprocessor and other digital devices in hardware, causing costly and somewhat large dimension system. In every practical application of energy conversion equipments, the design and implementation should be carried out considering cost and performance. High performance and low cost is the best choice for energy conversion equipments. So, this paper presents the practical design method and implementation results of 3-phase PWM Converter with analog hysteresis current controller, and verifies the performances of unit power factor operation and energy regeneration operation via experimental results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.281-283
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• 2016

Recently, many industrial instruments face the problem of protocol compatibility with the external monitoring and control system. This paper is prepared in the main control board to support the industrial communication protocol conversion, control, and monitoring. The industrial communication gateway module is also designed to ensure that the protocol conversion of CAN bus and Ethernet. The main board processor is used the Atmega2560, and placed 4ea RS485 serial slots for sub-board. One of them is used for communication CAN bus and Ethernet. It provides analog and digital I / O through each of the slots is used for control and monitoring.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.6
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• pp.726-731
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• 2004

This paper proposes a pulse-width-modulation (PWM) controller design technique using intelligent digital redesign. Intelligent digital redesign is to convert a well-designed analog fuzzy-model-based controller into an equivalent pulse-amplitude-modulation (PAM) digital controller maintaining the original analog control system in the sense of state-matching. In similar line of conversion concept, the redesigned PAM intelligent digital controller is converted into a PWM controller using the equivalent area principle. To convincingly visualize the proposed technique, an computer simulation example-attitude control of nonlinear artificial satellite system is included.

• Journal of Digital Convergence
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• v.11 no.6
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• pp.1-9
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• 2013

The digital signal is terminated on Dec.31, 2012. But most of the analog cable subscribers are faced with the difficult reception of the digital because the government has defined the terrestrial broadcast as digital transition obligation operators. It is estimated that half analog of the total pay-TV subscriber that is approximately 10million households that are directly receiving terrestrial signal must hold the digital TV or DtoA convertor to transit digital. But cable system subscriber should buy Set-top box that are expensive and pay the expensive rates. The cast of analog cable subscribers has been classified as a group that can cause the most damage after digital switch. This study investigate the problem, and cause, solution of the analog cable subscribers that are placed in the blind spots of the digital switch.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1701-1705
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• 2004

This paper presents a design and analysis of electromechanical sigma-delta modulator for MEMS gyroscope, which enables us to control the proof mass and to obtain an exact digital output without additional A/D conversion. The system structure and the circuit realization of the sigma-delta modulation are simpler than those of the analog sensing and feedback circuit. Based on the electrical sigma-delta modulator theory, a compensator is designed to improve the closed loop resolution of the sensor. With the designed compensator, we could obtain enhanced closed-loop performances of the gyroscope such as larger bandwidth, lower noise, and digital output comparing with the results of analog open-loop system.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.569-572
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• 2004

This paper presents a 12-Bit 250MHz CMOS current-mode Digital to Analog Converter(DAC) with current scalers and dividers. It consist of 4 MSB current scaler, 4 MLSB current divider, and 4 LSB current divider. The simulation results show a conversion rate of 250MHz, DNL/INL of ${\pm}5LSB/{\pm}7LSB$, die area of $0.55mm^2$ and Power dissipation of 27mW at 3.3V