• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.121-124
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• 2004

In this paper, Simple and inexpensive analog maximum power point tracker (MPPT) algorithm for photovoltaic power system and low power system of doesn't use digital signal processor (DSP). The control circuit is composed such that the actual current and voltage are sensed directly from the PV array. These two signals are then multiplied by a single-chip multiplier. The multiplier output go through different time constants genesis pulse width modulated to switch. Finally those were verified through simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.6
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• pp.584-591
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• 2004

The conventional analog-based firing circuit can be implemented by comparing a linearly decreasing periodic sawtooth waveform synchronized to the ac supply, with a control signal corresponding to the desired converter delay angle. This circuit requires a large number of passive components (resistance and capacitor) and careful adjustment of the synchronization circuity. In this paper a novel firing circuit is proposed for thyristor switch. The proposed circuit is implemented by using digital components(FPGA, A/D, and DSP etc.) on the basis of the analog cosine method.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.565-568
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• 2003

The conventional analog-based firing circuit can be implemented by comparing a linearly decreasing periodic sawtooth waveform synchronized to the ac line, with a voltage corresponding to the desired converter delay angle. This circuit requires a large number of components (resistance and capacitor) and careful adjustment of the synchronization circuity In this paper a novel firing circuit is proposed for thyristor switch is elements. The proposed circuit is implemented on the basis of the analog cosine method using FPGA and microprocessor.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.513-513
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• 2000

An integrable circuit technique for implementing high-speed analog two-input Max/Min circuit is described. The realization method is suitable for fabrication using CMOS technology. The proposed circuit comprises a current mirror and electronic switch connected with a absolute value circuit. The maximum or minimum operation of the proposed circuit can be selected by an external control voltage. The proposed analog Max/Min circuit has a very sharp transfer characteristic and is suitable for real-time systems. Simulation results verified the circuit performances are agreed with the expected values.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2002.10a
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• pp.330-337
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• 2002

The HANARO seismic monitoring system is classified as non-nuclear safety(NNS), seismic category I, and quality class T The seismic monitoring system installed at the instrument room consists of five field sensors and one monitoring cabinet. The field sensors are composed of three triaxial accelerometers which installed at base slab, free field and overhead crane support respectively, a seismic trigger and a seismic switch at base slab. The most parts of analog system except field sensors are not produced any more, the improvement of the system is to be needed. The analog system with magnetic tape recorder is not only out-of-date model but dependent upon foreign technology. So it is difficult to get the spare parts and the cost to buy them is increased. Therefore we have improved the analog seismic monitoring system into a new digital seismic monitoring analysis system(SMAS) except five field sensors. After the installation of the new SMAS, we have carried out the site acceptance test(SAT) to confirm the field functions. The results of SAT satisfy the requirements of the fabrication technical specification. This new SMAS is operating at HANARO instrument room to acquire and analyse the signal of earthquake.

• Journal of Biomedical Engineering Research
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• v.2 no.1
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• pp.55-64
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• 1981

The important parameters of DC amplifier, which is widely use4 for the medical and engineering fields, are input offset voltage and temperature drift. Chopping amplifier reduces approximately 10% the parameters changing than monolithic operational amplifier. In this study, a chopping amplifier with semiconductor chopper is designed and tested, this chopper is realized by CMOS analog switch and timing circuits. The test results approve that designed amplifier is suitable for precision instrument DC amplifier.

• Journal of Industrial Technology
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• v.26 no.B
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• pp.243-248
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• 2006

The purpose of this study is to design a body-fat measurable electronic scale which can measure body impedance and weight. The hardware configuration of this system for the body-fat measurement includes a sinewave constant current generator, a analog switch circuit and a microprocessor with peripheral interface as well as electronic scale circuit. And the dedicated software is also designed for calculating body fat and body composition analysis from the result of the measurement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.