• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.55-60
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• 2011

Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4ns for 32 data with 10-bit resolution in the simulation with 1.2V, $0.13{\mu}m$-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.747-750
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• 2004

The researching content of this article is to implement the image grabber system for use the dental hospital image examination. It receives the NTSC analog image through CCD optical camera, which is using the close photographing. we made the image grabber board, which gathers and obtains the analog image, by PCI format. We developed the C++ application and device drive to operate this board so that we totally could implement and confirm this Image grabber system.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.569-572
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• 2004

This paper presents a 12-Bit 250MHz CMOS current-mode Digital to Analog Converter(DAC) with current scalers and dividers. It consist of 4 MSB current scaler, 4 MLSB current divider, and 4 LSB current divider. The simulation results show a conversion rate of 250MHz, DNL/INL of ${\pm}5LSB/{\pm}7LSB$, die area of $0.55mm^2$ and Power dissipation of 27mW at 3.3V

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.17-26
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• 2006

The analog Viterbi decoder for the PR (1 2 2 1) which is used for BVD read channel is designed with circular analog parallel circuits. Since the inter symbol interference is serious problem in the high density magnetic storage device or DVD, the PRML technology is normally employed for the purpose of minimizing the decoding error. The feature of the PRML technology is with the multi-level coding according to the predetermined combining rule among the neighboring symbols and with the decoding according to the known combining rule. Though the conventional PRML technology is implemented with the digital circuits, the recent trend towards this end is with the utilization of the analog circuits due to the requirements of higher speed and lower power in the DVD read channel. In this study, the Viterbi decoder which is the bottleneck of the PRML implementation is designed with the analog parallel circuit structure. The designed Viterbi decoder for the PR (1 2 2 1) signal shows 3 times faster in the speed and 1/3 times less in the power consumption than thoseoftheconventionaldigitalcounterpart.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.212-215
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• 2000

This paper introduces to design analog circuits with Verilog-A. It is a tool for design and simulation of analog ICs in behavioral level. Verilog-A has been already established standard and used to IP development in USA. We have proved the possibility of Verilog-A by comparing with measurement data of a fabricated 235MHz PLL circuit. This paper also describes another advantage of Verilog-A.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.244-247
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• 1999

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.825-828
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• 1999

In this paper, we design the analog phase shifter for the elimination of the ghost signal. Compensation of the delay between the reference signal and the relatively delayed signal is possible. This phase shifter uses the vector summing method. We use for the attenuator in our system FETs. The phase shifter is operated at the 200MHz and composed by lumped elements. The proposed analog phase shifter is simulated by the HP ADS software.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.909-912
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• 1999

This paper describes realized APC and pre-equalizer circuit, and their operation principle and test results. In analog optical transmitter, constant lasing power control, free of signal clipping and linearity are important considerations. We examined pre-equalizer and APC(Automatic Power Control) circuit to improve the analog optical transmitter performance.