Design of Low voltage CMOS Analog Four-Quadrant Multiplier

저전압 CMOS 아날로그 4상한 멀티플라이어 설계

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.