• 대한전자공학회논문지SD
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• 제46권10호
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• pp.31-39
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• 2009

본 논문은 전력선 통신용(PLC) SoC ASIC으로 내장된 Analog Front-end(AFE)를 바탕으로 낮은 소비 전력과 저 가격을 달성할 수 있었으며, CMOS공정으로 구현된 AFE와, 1.8V동작의 Core Logic구동용 LDO, ADC, DAC와 IO pad를 구동하기 위한 LDO로 구성되어 있다. AFE는 Pre-amplifier, Programmable gain Amplifier와 10bit ADC의 수신 단으로 구성되며, 송신 단은 10bit differential DAC, Line Driver로 구성되어 있다. 본 ASIC은 0.18 um 1 Poly 5 Metal CMOS로 구현 되었으며, 동작전압은 3.3 V단일 전원만 사용하였고, 이때 소모 전력은 대기 시에 30mA이며, 동작 시 전력은 300mA으로 에코 디자인 요구를 만족하게 하였다. 본 칩의 Chip size는 $3.686\;{\times}\;2.633\;mm^2$ 이다.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.504-510
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• 2015

This paper presents a power and area efficient SAR ADC for multi-channel near threshold-voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive-array (S-DCA) structure with shifted input range for ultra low-switching energy and architecture of multi-channel single-ended SAR ADC which employs only one comparator. In addition, the proposed ADC has the same amount of equivalent capacitance at two comparator inputs, which minimizes the kickback noise. Compared with conventional SAR ADC, this work reduces the total capacitance and switching energy by 84.8% and 91.3%, respectively.

• 대한의용생체공학회:의공학회지
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• 제26권1호
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• pp.49-54
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• 2005

This paper presents a design of 1-channel active dry electrode module for EEG from one's forehead. The IA(instrumentation amplifier) circuit inside the module is based on the configuration sown on the paper MettingVanRijn et al. We analyze the IA circuit to find out the related equation, and then compare its simulated characteristic with the result obtained from the real active dry electrode circuit. With the active dry electrode and the wet(Ag/AgCI) electrode connected to the separated analog processing module on one's forehead at the same time, their real time and FFT outputs of EEG are examined for comparison. The active dry electrode module has advantages over the wet electrode and its analog processing module: 1) The size of the analog processing circuit of the active dry electrode module is smaller than that of existing EEG analog processing module; 2) the total cost required to make the proposed analog processing circuit is much lower than that of the existing circuit, since the designed circuit needs smaller parts; 3) the electrical characteristic is comparable to the general EEG analog processing module even if the designed module has simpler circuit configuration.

• ETRI Journal
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• 제25권3호
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• pp.195-202
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• 2003

This paper proposes a new LDMOSFET structure with a trenched sinker for high-power RF amplifiers. Using a low-temperature, deep-trench technology, we succeeded in drastically shrinking the sinker area to one-third the size of the conventional diffusion-type structure. The RF performance of the proposed device with a channel width of 5 mm showed a small signal gain of 16.5 dB and a maximum peak power of 32 dBm with a power-added efficiency of 25% at 2 GHz. Furthermore, the trench sinker, which was applied to the guard ring to suppress coupling between inductors, showed an excellent blocking performance below -40 dB at a frequency of up to 20 GHz. These results confirm that the proposed trenched sinker should be an effective technology both as a compact sinker for RF power devices and as a guard ring against coupling.

• ETRI Journal
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• 제42권4호
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• pp.534-548
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• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.341-344
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• 2002

This paper is proposed a 8-bit analog to digital converter for CMOS image sensor. A analog to digital converter for CMOS image sensor is required function to control gain. Frequency divider is used In control gain in this proposed analog to digital converter. At 3.3 Volt power supply, total static power dissipation is 8㎽ and programmable gain control range is 30㏈. Newly suggested analog to digital converter is designed by 0.35um 2-poly 4-metal CMOS technology.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1997년도 전력전자학술대회 논문집
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• pp.14-20
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• 1997

Due to several advantages of Pulse Width Modulated(PWM) Converter, such as unity power factor with low-harmonics and energy regeneration, PWM converter has been widely used in industrial application. In every application of energy conversion equipment, the design and implementation must be carried out considering performance and cost. High quality with low cost is the best choice for energy conversion equipment. High dc link voltage can reduce inverter and motor side losses and system dimension compare to low dc link voltage. Analog controller can make PWM converter cheaper without considerable degradation of the performance than digital controller. This paper shows the simplified analog controller-for 600V dc link voltage using stationary reference frame control and the simulation results.

• 전자공학회지
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• 제2권2호
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• pp.37-42
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• 1975

램프형 A/D 변환기의 직선도의 정밀도에 영향을 미치는 여러 가지 원인들을 실험적으로 고찰하였다. 아울러 램프형 A/D 변환기의 직선도, 정밀도, 및 상계오차를 개선하기 위한 회로소자의 결정방법을 제안하였다. Various factors which affect the linearity and accuracy of the ramp type analog-to-digital converter have been investigated experimentally. A suggestion hav been made in the determination of circuit parameters with the emphasis on the improvement of the linearity and accuracy in the ramp type analog-to-digital conveter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 추계학술대회 논문집
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• pp.66-67
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• 2014

Stabilization of the DC bus voltage is an important task in DC-AC microgrid system with renewable energy source such as solar system. A battery energy storage system (BESS) has become a general solution to stabilize the DC-bus voltage in DC-AC microgrid. This paper develops the analog BESS controller which requires neither computation nor dc-bus voltage measurement, so that the system can be implemented simply and easily. Even though others methods can stabilize and control the DC-bus voltage, it has complicated structure in control and low adaptive capability. The proposed topology is simple but is able to compensate the solar source variation and stabilize the DC-bus voltage under any loads and distributed generation (DG) conditions. In addition, the design of analog controller is presented to obtain a robust system. In order to verify the effectiveness of the proposed control strategy, simulation is carried out by using PSIM software.