• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

• Journal of IKEEE
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• v.22 no.2
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• pp.514-517
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• 2018

In sensor systems, ADC (analog-to-digital converter) demands high resolution, low power consumption, and high signal bandwidth. Sigma-delta ADC achieves high resolution by high order structure and high over-sampling ratio, but it suffers from high power consumption and low signal bandwidth. SAR (successive-approximation-register) ADC achieves low power consumption, but there is a limitation to achieve high resolution due to process mismatch. This paper surveys architecture improvement of ADC to overcome these problems.

• 한국초전도학회:학술대회논문집
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• v.11
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• pp.35-35
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• 2001

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.232-237
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• 2004

In many application of DC-DC converters, loads cannot be specified in advance, i.e., their amplitudes are suddenly changed from the zero to the maximum rating. Generally, design conditions are changed for each load and then each controller is re-designed. Then, a so-called robust DC-DC converter which can cover such extensive load changes and also input voltage changes with one controller is needed. Analog control IC is used usually for the controller of DC-DC converter. Simple integral control etc. are performed with the analog control IC. However it is difficult to retain sufficient robustness of DC-DC converter by these techniques. The authors proposed the method of designing an approximate 2-degree-of-freedom (2DOF) controller of DC-AC converter. This controller has an ability to attain sufficient robustness against extensive load and DC power supply changes. For applying this approximate 2DOF controller to DC-DC converter, it is necessary to improve the degree of approximation for better robustness. In this paper, we propose a method of designing good approximate 2DOF digital controller which makes the control bandwidth wider, and at the same time makes a variation of the output voltage very small at a sudden change of resistive load. The proposed good approximate 2DOF digital controller is actually implemented on a DSP and is connected to a DC-DC converter. Experimental studies demonstrate that this type digital controller can satisfy given specifications.

• The Journal of Korea Robotics Society
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• v.2 no.3
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• pp.205-211
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• 2007

In this paper, the prototype of surface EMG (ElectroMyoGram) sensor is developed for the robotic rehabilitation applications, and the developed sensor is composed of the electrodes, analog signal amplifiers, analog filters, ADC (analog to digital converter), and DSP (digital signal processor) for coding the application example. Since the raw EMG signal is very low voltage, it is amplified by about one thousand times. The artifacts of amplified EMG signal are removed by using the band-pass filter. Also, the processed analog EMG signal is converted into the digital form by using ADC embedded in DSP. The developed sensor shows approximately the linear characteristics between the amplitude values of the sensor signals measured from the biceps brachii of human upper arm and the joint angles of human elbow. Finally, to show the performance of the developed EMG sensor, we suggest the application example about the real-time human elbow motion acquisition by using the developed sensor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• International Journal of Internet, Broadcasting and Communication
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• v.5 no.2
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• pp.11-14
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• 2013

This paper describes the sigma-delta ADC/DAC digital block with two channels. The ADC block has comb filter and three half band filters. And the DAC block has 5th Cascaded-of-Integrators Feedback DSM. The ADC and DAC support I2S, RJ, LJ and selectable input data modes of 24bit, 20bit, and 16bit. It is fabricated with 0.35um Hynix standard CMOS cell library. The chip size is 3700*3700um. It has been verified using NC Verilog Simulator and Matlab Tool.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.3
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• pp.497-502
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• 2018

An analog to digital converter(: ADC) has been designed to extract video signals of marine X-band radar and convert to digital signals in order to produce rainfall information. X-band weather radars are suitable for high temporal-spatial resolution observations of rainfall over local ranges but they are very expensive and require professional management. The marine radars with 10-2 cost facilitate data collection and management as well as economic benefits. To validate the usefulness of the developed ADC, comparative observations were made with weather radar for short term precipitation cases. The rainfall distribution of marine radar observations are consistent with that of weather radar within a radius of 15 km. This demonstrates the usability of marine radar for rainfall observations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.378-384
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• 2013

In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a $0.25{\mu}m$ 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to $150^{\circ}C$. The area and power consumption of the fabricated temperature sensor are $130{\times}390{\mu}m^2$ and $868{\mu}W$, respectively.

• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.587-592
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• 2002

A new digital correlator fur an airborne synthetic aperture radiometer was designed in order to replace the conventional analog correlator unit which will become very complicated while the number of channels is increasing. The digital correlator uses digital IQ demodulator instead of the intermediate frequency (IF) phase shifter to make the correlation processing performed digitally at base band instead of analogly at IF. This technique has been applied to the digital receiver in softradio. The down-converted IF signals from each pair of receiver channels become low rate base-band digital signals after under-sampled, Digitally Down-Converted (DDC), decimated and filtered by FIR filters. The digital signals are further processed by two digital multipliers (complex correlation), the products are integrated by the integrators and finally the outputs from the integrators compose of the real part and the imaginary part of a sample of the visibility function. This design is tested by comparing the results from digital correlators and that from analog correlators. They are agreed with each other very well. Due to the fact that the digital correlators are realized with the help of Analog-Digital Converter (ADC) chips and the FPGA technology, the realized volume, mass, power consumption and complexity turned out to be greatly reduced compared with that of the analog correlators. Simulations show that the resolution of ADC has an influence on the synthesized antenna patterns, but this can be neglected if more than 2bit is used.